From 0545a32e2e830249e00fe8b693f1b1a2132b2148 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Fri, 5 Jan 2024 16:46:20 +0100 Subject: [PATCH] chore: update constraints for master ssd1306 --- .../constrs_1/new/constraints.xdc | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/vivado/nsv_i2c.srcs/constrs_1/new/constraints.xdc b/vivado/nsv_i2c.srcs/constrs_1/new/constraints.xdc index 6da187ecb739b63c2484b94b966b83bcfdcf1cc4..72d55317c49383e7858f793e34e186e394708f76 100644 --- a/vivado/nsv_i2c.srcs/constrs_1/new/constraints.xdc +++ b/vivado/nsv_i2c.srcs/constrs_1/new/constraints.xdc @@ -53,37 +53,37 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk ## LEDs -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports err_noack_o] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports bus_busy_o] set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports dev_busy_o] -set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports bus_busy_o] +set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports err_noack_address_o] -set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports rst_on] +set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports err_noack_data_o] -#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}] +set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports err_arbitration_o] -#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}] +set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports err_general_o] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports waiting_o] #set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}] #set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] -#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] +set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {full_on_state_o[0]}] -#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] +set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {full_on_state_o[1]}] -#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] +set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {full_on_state_o[2]}] -#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {state_o[0]}] -#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {state_o[1]}] -#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {state_o[2]}] -#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {state_o[3]}] @@ -121,7 +121,7 @@ set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports rst_on] set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports rst_i] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports start_i] #set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL] @@ -287,4 +287,4 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] -set_property CONFIG_MODE SPIx4 [current_design] \ No newline at end of file +set_property CONFIG_MODE SPIx4 [current_design]