From b2a16253799b551632b163adeb92c42db6a6da07 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Mon, 12 Feb 2024 16:39:43 +0100
Subject: [PATCH] tests: add dac model

---
 tb/model/tb_dac_mod.vhd | 55 +++++++++++++++++++++++++++++++++++++++++
 tb/model/tb_dac_pkg.vhd | 46 ++++++++++++++++++++++++++++++++++
 tb/test.vhd             | 10 ++++++++
 3 files changed, 111 insertions(+)
 create mode 100644 tb/model/tb_dac_mod.vhd
 create mode 100644 tb/model/tb_dac_pkg.vhd

diff --git a/tb/model/tb_dac_mod.vhd b/tb/model/tb_dac_mod.vhd
new file mode 100644
index 0000000..6ed3917
--- /dev/null
+++ b/tb/model/tb_dac_mod.vhd
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+use ieee.numeric_std.all;
+
+library vunit_lib;
+context vunit_lib.com_context;
+
+use work.tb_dac_pkg.all;
+
+entity tb_dac_mod is
+
+  generic (
+    inst_name : string := C_DEFAULT_INST_NAME;
+    resolution : natural);
+
+  port (
+    clk_i    : in  std_logic;
+    signal_i : in  std_logic_vector(resolution - 1 downto 0);
+    signal_o : out real);
+
+end entity tb_dac_mod;
+
+architecture behav of tb_dac_mod is
+  signal min : real := -1.0;
+  signal max : real := 1.0;
+
+  signal reconstructed : real := 0.0;
+begin  -- architecture behav
+  signal_o <= reconstructed;
+
+  sample: process (clk_i) is
+  begin  -- process out
+    if rising_edge(clk_i) then          -- rising clock edge
+      reconstructed <= real(to_integer(unsigned(signal_i))) / real(2 ** RESOLUTION - 1) * (max - min) + min;
+    end if;
+  end process sample;
+
+  message_handler: process is
+    constant actor : actor_t := new_actor(inst_name);
+    variable request_msg : msg_t;
+    variable msg_type : msg_type_t;
+  begin  -- process message_handler
+    receive(net, actor, request_msg);
+    msg_type := message_type(request_msg);
+
+    if msg_type = set_min_max_msg then
+      min <= pop(request_msg);
+      max <= pop(request_msg);
+    else
+      unexpected_msg_type(msg_type);
+    end if;
+  end process message_handler;
+
+end architecture behav;
diff --git a/tb/model/tb_dac_pkg.vhd b/tb/model/tb_dac_pkg.vhd
new file mode 100644
index 0000000..9f9f24d
--- /dev/null
+++ b/tb/model/tb_dac_pkg.vhd
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library vunit_lib;
+context vunit_lib.com_context;
+
+package tb_dac_pkg is
+
+  constant C_DEFAULT_INST_NAME : string := "dac_mod";
+
+  constant set_min_max_msg : msg_type_t := new_msg_type("dac set min max");
+
+  impure function get_actor (
+    constant inst_name : string := C_DEFAULT_INST_NAME)
+    return actor_t;
+
+  procedure set_min_max (
+    signal net : inout network_t;
+    constant min : in real;
+    constant max : in real;
+    constant actor : in actor_t := get_actor);
+
+end package tb_dac_pkg;
+
+package body tb_dac_pkg is
+
+  impure function get_actor (
+    constant inst_name : string := C_DEFAULT_INST_NAME)
+    return actor_t is
+  begin
+    return find(inst_name);
+  end function get_actor;
+
+  procedure set_min_max (
+    signal net     : inout network_t;
+    constant min   : in    real;
+    constant max   : in    real;
+    constant actor : in    actor_t := get_actor) is
+    variable msg : msg_t := new_msg(set_min_max_msg);
+  begin
+    push(msg, min);
+    push(msg, max);
+    send(net, actor, msg);
+  end procedure set_min_max;
+
+end package body tb_dac_pkg;
diff --git a/tb/test.vhd b/tb/test.vhd
index 818a74c..cebc7cd 100644
--- a/tb/test.vhd
+++ b/tb/test.vhd
@@ -8,6 +8,7 @@ context vunit_lib.com_context;
 use work.tb_sig_adder_pkg;
 use work.tb_sig_gen_pkg;
 use work.tb_adc_pkg;
+use work.tb_dac_pkg;
 
 library filter;
 
@@ -51,6 +52,7 @@ begin  -- architecture tb
         tb_sig_gen_pkg.set_shape(net, tb_sig_gen_pkg.SIG_SHAPE_SINE, actor => generator);
 
         tb_adc_pkg.set_min_max(net, -2.0, 2.0);
+        tb_dac_pkg.set_min_max(net, -2.0, 2.0);
         tb_adc_pkg.set_sampling_rate(net, frequency);
         tb_adc_pkg.run(net);
 
@@ -88,6 +90,14 @@ begin  -- architecture tb
       signal_o       => sampled_sig,
       current_time_o => current_time);
 
+  dac: entity work.tb_dac_mod
+    generic map (
+      RESOLUTION => resolution)
+    port map (
+      clk_i          => clk,
+      signal_i       => filtered_sig,
+      signal_o       => reconstructed_sig);
+
   xtal: entity work.tb_xtal_mod
     generic map (
       default_frequency => frequency)
-- 
2.48.1