~ruther/verilog-riscv-semestral-project

ref: 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 498 bytes 
fix: offset ram by bytes, not bits

feat: implement sb, sh, lb, lh support via masking

feat: add basic ram, alu, and register file