From e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Sun, 29 Oct 2023 19:35:42 +0100
Subject: [PATCH] test: add cpu testbenches for c programs

---
 testbench/tb_cpu_add.sv      | 58 ++++++++++++++++++++++++++++++++++++
 testbench/tb_cpu_branches.sv | 57 +++++++++++++++++++++++++++++++++++
 testbench/tb_cpu_gcd.sv      | 57 +++++++++++++++++++++++++++++++++++
 testbench/tb_cpu_tests.sv    | 57 +++++++++++++++++++++++++++++++++++
 4 files changed, 229 insertions(+)
 create mode 100755 testbench/tb_cpu_add.sv
 create mode 100755 testbench/tb_cpu_branches.sv
 create mode 100755 testbench/tb_cpu_gcd.sv
 create mode 100755 testbench/tb_cpu_tests.sv

diff --git a/testbench/tb_cpu_add.sv b/testbench/tb_cpu_add.sv
new file mode 100755
index 0000000..3aaa50a
--- /dev/null
+++ b/testbench/tb_cpu_add.sv
@@ -0,0 +1,58 @@
+
+import cpu_types::*;
+
+module tb_cpu_add();
+  reg clk, rst_n;
+
+  wire [31:0] memory_address, memory_write, memory_out;
+  wire        memory_we;
+
+  memory_mask_t memory_mask;
+
+  wire [31:0] pc;
+  reg [31:0]  instruction;
+
+  cpu uut(
+    .clk(clk),
+    .rst_n(rst_n),
+
+    .instruction(instruction),
+    .pc(pc),
+
+    .memory_address(memory_address),
+    .memory_out(memory_out),
+    .memory_write(memory_write),
+    .memory_mask(memory_mask),
+    .memory_we(memory_we)
+  );
+
+  ram memory_inst(
+    .clk(clk),
+    .a(memory_address),
+    .mask(memory_mask),
+    .we(memory_we),
+    .wd(memory_write),
+    .rd(memory_out)
+  );
+
+  file_program_memory #(.FILE_NAME("programs/bin/add.dat")) prog_mem_inst(
+    .addr(pc[11:0]),
+    .instruction(instruction)
+  );
+
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
+
+  initial begin
+    $dumpfile("waves/tb_cpu_add.vcd");
+    $dumpvars;
+
+    rst_n = 0;
+    #20
+    rst_n = 1;
+
+    #500 $finish;
+  end
+endmodule
diff --git a/testbench/tb_cpu_branches.sv b/testbench/tb_cpu_branches.sv
new file mode 100755
index 0000000..0a78fb4
--- /dev/null
+++ b/testbench/tb_cpu_branches.sv
@@ -0,0 +1,57 @@
+import cpu_types::*;
+
+module tb_cpu_branches();
+  reg clk, rst_n;
+
+  wire [31:0] memory_address, memory_write, memory_out;
+  wire        memory_we;
+
+  memory_mask_t memory_mask;
+
+  wire [31:0] pc;
+  reg [31:0]  instruction;
+
+  cpu uut(
+    .clk(clk),
+    .rst_n(rst_n),
+
+    .instruction(instruction),
+    .pc(pc),
+
+    .memory_address(memory_address),
+    .memory_out(memory_out),
+    .memory_write(memory_write),
+    .memory_mask(memory_mask),
+    .memory_we(memory_we)
+  );
+
+  ram memory_inst(
+    .clk(clk),
+    .a(memory_address),
+    .mask(memory_mask),
+    .we(memory_we),
+    .wd(memory_write),
+    .rd(memory_out)
+  );
+
+  file_program_memory #(.FILE_NAME("programs/bin/branches.dat")) prog_mem_inst(
+    .addr(pc[11:0]),
+    .instruction(instruction)
+  );
+
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
+
+  initial begin
+    $dumpfile("waves/tb_cpu_branches.vcd");
+    $dumpvars;
+
+    rst_n = 0;
+    #20
+    rst_n = 1;
+
+    #500 $finish;
+  end
+endmodule
diff --git a/testbench/tb_cpu_gcd.sv b/testbench/tb_cpu_gcd.sv
new file mode 100755
index 0000000..527d027
--- /dev/null
+++ b/testbench/tb_cpu_gcd.sv
@@ -0,0 +1,57 @@
+import cpu_types::*;
+
+module tb_cpu_gcd();
+  reg clk, rst_n;
+
+  wire [31:0] memory_address, memory_write, memory_out;
+  wire        memory_we;
+
+  memory_mask_t memory_mask;
+
+  wire [31:0] pc;
+  reg [31:0]  instruction;
+
+  cpu uut(
+    .clk(clk),
+    .rst_n(rst_n),
+
+    .instruction(instruction),
+    .pc(pc),
+
+    .memory_address(memory_address),
+    .memory_out(memory_out),
+    .memory_write(memory_write),
+    .memory_mask(memory_mask),
+    .memory_we(memory_we)
+  );
+
+  ram memory_inst(
+    .clk(clk),
+    .a(memory_address),
+    .mask(memory_mask),
+    .we(memory_we),
+    .wd(memory_write),
+    .rd(memory_out)
+  );
+
+  file_program_memory #(.FILE_NAME("programs/bin/gcd.dat")) prog_mem_inst(
+    .addr(pc[11:0]),
+    .instruction(instruction)
+  );
+
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
+
+  initial begin
+    $dumpfile("waves/tb_cpu_gcd.vcd");
+    $dumpvars;
+
+    rst_n = 0;
+    #20
+    rst_n = 1;
+
+    #5000 $finish;
+  end
+endmodule
diff --git a/testbench/tb_cpu_tests.sv b/testbench/tb_cpu_tests.sv
new file mode 100755
index 0000000..6d1464a
--- /dev/null
+++ b/testbench/tb_cpu_tests.sv
@@ -0,0 +1,57 @@
+import cpu_types::*;
+
+module tb_cpu_tests();
+  reg clk, rst_n;
+
+  wire [31:0] memory_address, memory_write, memory_out;
+  wire        memory_we;
+
+  memory_mask_t memory_mask;
+
+  wire [31:0] pc;
+  reg [31:0]  instruction;
+
+  cpu uut(
+    .clk(clk),
+    .rst_n(rst_n),
+
+    .instruction(instruction),
+    .pc(pc),
+
+    .memory_address(memory_address),
+    .memory_out(memory_out),
+    .memory_write(memory_write),
+    .memory_mask(memory_mask),
+    .memory_we(memory_we)
+  );
+
+  ram memory_inst(
+    .clk(clk),
+    .a(memory_address),
+    .mask(memory_mask),
+    .we(memory_we),
+    .wd(memory_write),
+    .rd(memory_out)
+  );
+
+  file_program_memory #(.FILE_NAME("programs/bin/tests.dat")) prog_mem_inst(
+    .addr(pc[11:0]),
+    .instruction(instruction)
+  );
+
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
+
+  initial begin
+    $dumpfile("waves/tb_cpu_tests.vcd");
+    $dumpvars;
+
+    rst_n = 0;
+    #20
+    rst_n = 1;
+
+    #500 $finish;
+  end
+endmodule
-- 
2.48.1