From db85fb354b873f3ab5e5e936b4412a7d828f0ca7 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Sat, 18 Nov 2023 14:26:00 +0100
Subject: [PATCH] tests: fix ram and control_unit tests to match newest
 architecture

---
 testbench/tb_control_unit.sv |  5 ++++-
 testbench/tb_ram.sv          | 25 +++++++++++++++++++------
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/testbench/tb_control_unit.sv b/testbench/tb_control_unit.sv
index 484ddb8..f8c2288 100755
--- a/testbench/tb_control_unit.sv
+++ b/testbench/tb_control_unit.sv
@@ -30,6 +30,8 @@ module tb_control_unit();
   memory_mask_t memory_mask;
   wire memory_sign_extension;
 
+  wire ebreak;
+
   control_unit uut(
     .instruction(instruction),
     .memory_we(memory_we),
@@ -49,7 +51,8 @@ module tb_control_unit();
     .reg_rd(reg_rd),
     .reg_we(reg_we),
     .memory_mask(memory_mask),
-    .memory_sign_extension(memory_sign_extension)
+    .memory_sign_extension(memory_sign_extension),
+    .ebreak(ebreak)
   );
 
   initial begin
diff --git a/testbench/tb_ram.sv b/testbench/tb_ram.sv
index d27ea64..436456b 100755
--- a/testbench/tb_ram.sv
+++ b/testbench/tb_ram.sv
@@ -1,25 +1,27 @@
 import cpu_types::*;
 
 module tb_ram();
-
   reg clk;
 
   reg [31:0] a;
 
   wire [31:0] rd;
 
-  memory_mask_t mask;
-
+  reg [3:0]  write_byte_enable;
   reg         we;
   reg [31:0]  wd;
 
+  reg         dump;
+
+
   ram uut(
     .clk(clk),
     .a(a),
     .rd(rd),
-    .mask(mask),
     .we(we),
-    .wd(wd)
+    .wd(wd),
+    .dump(dump),
+    .write_byte_enable(write_byte_enable)
   );
 
   initial begin
@@ -31,9 +33,11 @@ module tb_ram();
     $dumpfile("waves/tb_ram.vcd");
     $dumpvars;
 
+    write_byte_enable = 4'b1111;
+
+
     #10
     a = 32'd103;
-    mask = MEM_WORD;
     we = 1;
     wd = 32'h5;
 
@@ -51,6 +55,15 @@ module tb_ram();
     we = 0;
     a = 32'd107;
 
+    #10
+    we = 1;
+    write_byte_enable = 4'b1100;
+
+    wd = 32'hFFFFFFFF;
+
+    #10
+    we = 0;
+
     #10 $finish;
   end
 
-- 
2.48.1