From c682cc068ee41da1b00fbd51dfb79f9cd5560d0d Mon Sep 17 00:00:00 2001 From: Rutherther Date: Sun, 5 Nov 2023 21:10:51 +0100 Subject: [PATCH] feat: implement ebreak Breaks the processor, can exit the testcase --- src/control_unit.sv | 6 +++++- src/cpu.sv | 27 +++++++++++++++++---------- src/instruction_decoder.sv | 9 ++++++++- testbench/tb_cpu_add.sv | 12 +++++++++--- testbench/tb_cpu_branches.sv | 12 +++++++++--- testbench/tb_cpu_gcd.sv | 12 +++++++++--- testbench/tb_cpu_simple.sv | 12 +++++++++--- testbench/tb_cpu_tests.sv | 12 +++++++++--- 8 files changed, 75 insertions(+), 27 deletions(-) diff --git a/src/control_unit.sv b/src/control_unit.sv index 4484e2c..4135e2a 100755 --- a/src/control_unit.sv +++ b/src/control_unit.sv @@ -35,7 +35,9 @@ module control_unit( // alu or memory output reg_rd_source_t reg_rd_src, output [4:0] reg_rd, - output reg_we + output reg_we, + + output ebreak ); wire use_immediate; @@ -54,6 +56,8 @@ module control_unit( instruction_decoder decoder( .instruction(instruction), + .ebreak(ebreak), + .store_memory(memory_we), .load_memory(load_memory), diff --git a/src/cpu.sv b/src/cpu.sv index 54446e7..10d8bdf 100755 --- a/src/cpu.sv +++ b/src/cpu.sv @@ -13,7 +13,9 @@ module cpu( input [31:0] memory_out, output reg [31:0] memory_write, output [3:0] memory_byte_enable, - output reg memory_we + output reg memory_we, + + output ebreak ); parameter WIDTH = 32; @@ -92,15 +94,18 @@ module cpu( // pc source assign jump_taken = jump_instruction && (alu_zero ^ jump_negate_zero); always_comb begin - case (pc_src) - PC_PLUS : begin - if (jump_taken) - pc_next = pc + immediate; - else - pc_next = pc + 4; - end - PC_ALU : pc_next = alu_out; - endcase + if (ebreak) + pc_next = pc; + else + case (pc_src) + PC_PLUS : begin + if (jump_taken) + pc_next = pc + immediate; + else + pc_next = pc + 4; + end + PC_ALU : pc_next = alu_out; + endcase end // register file write source @@ -117,6 +122,8 @@ module cpu( control_unit control_unit_inst( .instruction(instruction), + .ebreak(ebreak), + .immediate(immediate), .alu_op(alu_op), diff --git a/src/instruction_decoder.sv b/src/instruction_decoder.sv index a33dd79..9b02671 100755 --- a/src/instruction_decoder.sv +++ b/src/instruction_decoder.sv @@ -47,7 +47,9 @@ module instruction_decoder( output [4:0] reg_rs1, output reg [4:0] reg_rs2, output [4:0] reg_rd, - output reg_we + output reg_we, + + output reg ebreak ); typedef enum bit[2:0] {Unknown, R, I, S, SB, U, UJ} instruction_type_type; instruction_type_type instruction_type; @@ -199,6 +201,7 @@ module instruction_decoder( reg_we = 1'b1; conditional_jump = 1'b0; unconditional_jump = 1'b0; + ebreak = 1'b0; // TODO: multiplication // NOTE: ecall, ebreak, CSRRW, CSRRS, SCRRC, CSRRWI, CSRRSI, CSRRCI unsupported @@ -232,6 +235,10 @@ module instruction_decoder( load_pc = 1'b1; reg_we = 1'b1; end + 5'b11100 : begin + if (funct3 == 3'b0) + ebreak = 1'b1; + end default : ; endcase; end; diff --git a/testbench/tb_cpu_add.sv b/testbench/tb_cpu_add.sv index 005a841..74be2a7 100755 --- a/testbench/tb_cpu_add.sv +++ b/testbench/tb_cpu_add.sv @@ -11,6 +11,8 @@ module tb_cpu_add(); wire [31:0] pc; reg [31:0] instruction; + wire ebreak; + cpu uut( .clk(clk), .rst_n(rst_n), @@ -22,7 +24,9 @@ module tb_cpu_add(); .memory_out(memory_out), .memory_write(memory_write), .memory_byte_enable(memory_write_byte_enable), - .memory_we(memory_we) + .memory_we(memory_we), + + .ebreak(ebreak) ); ram memory_inst( @@ -39,6 +43,10 @@ module tb_cpu_add(); .instruction(instruction) ); + always_ff @ (posedge ebreak) begin + #15 $finish; + end + initial begin clk = 0; forever #5 clk = ~clk; @@ -51,7 +59,5 @@ module tb_cpu_add(); rst_n = 0; #20 rst_n = 1; - - #500 $finish; end endmodule diff --git a/testbench/tb_cpu_branches.sv b/testbench/tb_cpu_branches.sv index e976cd9..01bb993 100755 --- a/testbench/tb_cpu_branches.sv +++ b/testbench/tb_cpu_branches.sv @@ -10,6 +10,8 @@ module tb_cpu_branches(); wire [31:0] pc; reg [31:0] instruction; + wire ebreak; + cpu uut( .clk(clk), .rst_n(rst_n), @@ -21,7 +23,9 @@ module tb_cpu_branches(); .memory_out(memory_out), .memory_write(memory_write), .memory_byte_enable(memory_write_byte_enable), - .memory_we(memory_we) + .memory_we(memory_we), + + .ebreak(ebreak) ); ram memory_inst( @@ -38,6 +42,10 @@ module tb_cpu_branches(); .instruction(instruction) ); + always_ff @ (posedge ebreak) begin + #15 $finish; + end + initial begin clk = 0; forever #5 clk = ~clk; @@ -50,7 +58,5 @@ module tb_cpu_branches(); rst_n = 0; #20 rst_n = 1; - - #500 $finish; end endmodule diff --git a/testbench/tb_cpu_gcd.sv b/testbench/tb_cpu_gcd.sv index e0fa1a5..88bb4d2 100755 --- a/testbench/tb_cpu_gcd.sv +++ b/testbench/tb_cpu_gcd.sv @@ -10,6 +10,8 @@ module tb_cpu_gcd(); wire [31:0] pc; reg [31:0] instruction; + wire ebreak; + cpu uut( .clk(clk), .rst_n(rst_n), @@ -21,7 +23,9 @@ module tb_cpu_gcd(); .memory_out(memory_out), .memory_write(memory_write), .memory_byte_enable(memory_write_byte_enable), - .memory_we(memory_we) + .memory_we(memory_we), + + .ebreak(ebreak) ); ram memory_inst( @@ -38,6 +42,10 @@ module tb_cpu_gcd(); .instruction(instruction) ); + always_ff @ (posedge ebreak) begin + #15 $finish; + end + initial begin clk = 0; forever #5 clk = ~clk; @@ -50,7 +58,5 @@ module tb_cpu_gcd(); rst_n = 0; #20 rst_n = 1; - - #5000 $finish; end endmodule diff --git a/testbench/tb_cpu_simple.sv b/testbench/tb_cpu_simple.sv index 88e0bdb..9fbe61e 100755 --- a/testbench/tb_cpu_simple.sv +++ b/testbench/tb_cpu_simple.sv @@ -11,6 +11,8 @@ module tb_cpu_simple(); wire [31:0] pc; reg [31:0] instruction; + wire ebreak; + cpu uut( .clk(clk), .rst_n(rst_n), @@ -22,7 +24,9 @@ module tb_cpu_simple(); .memory_out(memory_out), .memory_write(memory_write), .memory_byte_enable(memory_write_byte_enable), - .memory_we(memory_we) + .memory_we(memory_we), + + .ebreak(ebreak) ); ram memory_inst( @@ -34,6 +38,10 @@ module tb_cpu_simple(); .rd(memory_out) ); + always_ff @ (posedge ebreak) begin + #15 $finish; + end + always_comb begin case(pc[5:2]) // addi x2, x0, 30 @@ -92,7 +100,5 @@ module tb_cpu_simple(); rst_n = 0; #20 rst_n = 1; - - #300 $finish; end endmodule diff --git a/testbench/tb_cpu_tests.sv b/testbench/tb_cpu_tests.sv index 4a5c4da..708ff9e 100755 --- a/testbench/tb_cpu_tests.sv +++ b/testbench/tb_cpu_tests.sv @@ -10,6 +10,8 @@ module tb_cpu_tests(); wire [31:0] pc; reg [31:0] instruction; + wire ebreak; + cpu uut( .clk(clk), .rst_n(rst_n), @@ -21,7 +23,9 @@ module tb_cpu_tests(); .memory_out(memory_out), .memory_write(memory_write), .memory_byte_enable(memory_write_byte_enable), - .memory_we(memory_we) + .memory_we(memory_we), + + .ebreak(ebreak) ); ram memory_inst( @@ -38,6 +42,10 @@ module tb_cpu_tests(); .instruction(instruction) ); + always_ff @ (posedge ebreak) begin + #15 $finish; + end + initial begin clk = 0; forever #5 clk = ~clk; @@ -50,7 +58,5 @@ module tb_cpu_tests(); rst_n = 0; #20 rst_n = 1; - - #500 $finish; end endmodule -- 2.48.1