From 69ced879bbbaf6d106ac95a8ee8e6a6872177c83 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Fri, 27 Oct 2023 11:00:55 +0200
Subject: [PATCH] fix: make rd1, rd2 in register_file regs

---
 src/register_file.sv | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/register_file.sv b/src/register_file.sv
index 23c24381f25ac8d1e2a5134431b9a9625dc1528c..7939996d8a9e8a683204ac55063773dac39e9d8a 100755
--- a/src/register_file.sv
+++ b/src/register_file.sv
@@ -8,8 +8,8 @@ module register_file(clk, a1, a2, a3, we3, wd3, rd1, rd2);
   input       we3; // write enable
   input [31:0] wd3; // write data
 
-  output [31:0] rd1;
-  output [31:0] rd2;
+  output reg [31:0] rd1;
+  output reg [31:0] rd2;
 
   reg [31:0]    gprs [32];
 
@@ -35,4 +35,3 @@ module register_file(clk, a1, a2, a3, we3, wd3, rd1, rd2);
   end
 
 endmodule
-//