From 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Sun, 29 Oct 2023 10:03:50 +0100
Subject: [PATCH] test: add ram test

---
 testbench/tb_ram.sv | 58 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100755 testbench/tb_ram.sv

diff --git a/testbench/tb_ram.sv b/testbench/tb_ram.sv
new file mode 100755
index 0000000000000000000000000000000000000000..d27ea64f3cce01345345a13cb1a796fa6b6e3e5c
--- /dev/null
+++ b/testbench/tb_ram.sv
@@ -0,0 +1,58 @@
+import cpu_types::*;
+
+module tb_ram();
+
+  reg clk;
+
+  reg [31:0] a;
+
+  wire [31:0] rd;
+
+  memory_mask_t mask;
+
+  reg         we;
+  reg [31:0]  wd;
+
+  ram uut(
+    .clk(clk),
+    .a(a),
+    .rd(rd),
+    .mask(mask),
+    .we(we),
+    .wd(wd)
+  );
+
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
+
+  initial begin
+    $dumpfile("waves/tb_ram.vcd");
+    $dumpvars;
+
+    #10
+    a = 32'd103;
+    mask = MEM_WORD;
+    we = 1;
+    wd = 32'h5;
+
+    #10
+    a = 32'd107;
+    we = 1;
+    wd = 32'h1;
+
+    #10
+    wd = 32'h0;
+    we = 0;
+    a = 32'd103;
+
+    #10
+    we = 0;
+    a = 32'd107;
+
+    #10 $finish;
+  end
+
+
+endmodule