3 files changed, 19 insertions(+), 7 deletions(-)

M include/clocks.h
M src/clocks.c
M src/main.c

@@ 34,7 34,8 @@ void clocks_enable(clock_t clock);
 bool clocks_ready(clock_t clock);
 void clocks_wait_ready(clock_t clock);
 
-void clocks_pll_configure(clock_pll_t pll, uint8_t divm, pll_source_t source,
+void clocks_pll_configure(clock_pll_t pll, uint8_t vcosel,
+                          uint8_t divm, pll_source_t source,
                           uint16_t divn, uint8_t divp, uint8_t divq,
                           uint8_t divr);
 void clocks_pll_enable(clock_pll_t pll);

@@ 40,11 40,23 @@ void clocks_wait_ready(clock_t clock) {
   while (!clocks_ready(clock));
 }
 
-void clocks_pll_configure(clock_pll_t pll, uint8_t divm, pll_source_t source,
+void clocks_pll_configure(clock_pll_t pll, uint8_t vcosel,
+                          uint8_t divm, pll_source_t source,
                           uint16_t divn, uint8_t divp, uint8_t divq,
                           uint8_t divr) {
   clocks_pll_disable(pll);
 
+
+  bool enable_p = divp > 0;
+  bool enable_q = divq > 0;
+  bool enable_r = divr > 0;
+
+  reg_write_bits_pos(&RCC->PLLCFGR,
+                     (enable_p << 0) | (enable_q << 1) | (enable_r << 2),
+                     3*pll + RCC_PLLCFGR_DIVR1EN_Pos, 0x7);
+
+  reg_write_bits_pos(&RCC->PLLCFGR, vcosel, (4*pll + RCC_PLLCFGR_PLL1VCOSEL_Pos), 1);
+
   reg_write_bits_pos(&RCC->PLLCKSELR, divm, RCC_PLLCKSELR_DIVM1_Pos + ((pll << 1) << 3), 0x3F);
   reg_write_bits_pos(&RCC->PLLCKSELR, source, RCC_PLLCKSELR_PLLSRC_Pos, 0x3);
 

@@ 80,11 80,10 @@ void main()
   clocks_enable(CLOCK_HSE);
   clocks_wait_ready(CLOCK_HSE);
 
-  // HSE 25 MHz -> divide by 25 -> 1 MHz
+  // HSE 25 MHz -> divide by 25 -> 1 MHz -> need VCOSEL 1
   // HSE / 25 * 400 = FVCO = 400 MHz
   // PLL2 R = 200 MHz
-  reg_set_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL_Msk);
-  clocks_pll_configure(CLOCK_PLL2, 25, PLL_SOURCE_HSE, 400, 2, 2, 2);
+  clocks_pll_configure(CLOCK_PLL2, 1, 25, PLL_SOURCE_HSE, 400, 2, 2, 2);
   clocks_pll_enable(CLOCK_PLL2);
   clocks_pll_wait_ready(CLOCK_PLL2, 300);
 


@@ 264,9 263,9 @@ void main()
     fmc_sdram_configure(&fmc, SDRAM_BANK2, sdram_config, sdram_timing, sdram_mode_register);
   }
 
-  uint32_t* sdram_data = (uint32_t*)fmc_sdram_allocate(&fmc, SDRAM_BANK2, 1024);
+  uint8_t* sdram_data = (uint8_t*)fmc_sdram_allocate(&fmc, SDRAM_BANK2, 1024);
 
-  for (uint32_t i = 0; i < 1024/4; i++) {
+  for (uint32_t i = 0; i < 1024; i++) {
     *(sdram_data + i) = i;
   }