M builddefs/common_features.mk => builddefs/common_features.mk +1 -1
@@ 212,7 212,7 @@ else
ifeq ($(PLATFORM),AVR)
# Automatically provided by avr-libc, nothing required
else ifeq ($(PLATFORM),CHIBIOS)
- ifneq ($(filter STM32F3xx_% STM32F1xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),)
+ ifneq ($(filter STM32F3xx_% STM32F1xx_% STM32F4xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),)
# Emulated EEPROM
OPT_DEFS += -DEEPROM_DRIVER -DEEPROM_STM32_FLASH_EMULATED
COMMON_VPATH += $(PLATFORM_PATH)/$(PLATFORM_KEY)/$(DRIVER_DIR)/flash
M data/mappings/defaults.json => data/mappings/defaults.json +6 -0
@@ 54,6 54,12 @@
"processor": "STM32F411",
"bootloader": "stm32-dfu",
"board": "BLACKPILL_STM32_F411"
+ },
+ "stemcell": {
+ "processor": "STM32F411",
+ "bootloader": "tinyuf2",
+ "board": "STEMCELL",
+ "pin_compatible": "promicro"
}
}
}
M docs/feature_converters.md => docs/feature_converters.md +22 -0
@@ 15,6 15,7 @@ Currently the following converters are available:
| `promicro` | `promicro_rp2040` |
| `promicro` | `blok` |
| `promicro` | `bit_c_pro` |
+| `promicro` | `stemcell` |
See below for more in depth information on each converter.
@@ 56,6 57,7 @@ If a board currently supported in QMK uses a [Pro Micro](https://www.sparkfun.co
| [SparkFun Pro Micro - RP2040](https://www.sparkfun.com/products/18288) | `promicro_rp2040` |
| [Blok](https://boardsource.xyz/store/628b95b494dfa308a6581622) | `blok` |
| [Bit-C PRO](https://nullbits.co/bit-c-pro) | `bit_c_pro` |
+| [STeMCell](https://github.com/megamind4089/STeMCell) | `stemcell` |
Converter summary:
@@ 66,6 68,7 @@ Converter summary:
| `promicro_rp2040` | `-e CONVERT_TO=promicro_rp2040` | `CONVERT_TO=promicro_rp2040` | `#ifdef CONVERT_TO_PROMICRO_RP2040` |
| `blok` | `-e CONVERT_TO=blok` | `CONVERT_TO=blok` | `#ifdef CONVERT_TO_BLOK` |
| `bit_c_pro` | `-e CONVERT_TO=bit_c_pro` | `CONVERT_TO=bit_c_pro` | `#ifdef CONVERT_TO_BIT_C_PRO` |
+| `stemcell` | `-e CONVERT_TO=stemcell` | `CONVERT_TO=stemcell` | `#ifdef CONVERT_TO_STEMCELL` |
### Proton C :id=proton_c
@@ 99,3 102,22 @@ The following defaults are based on what has been implemented for [RP2040](platf
### SparkFun Pro Micro - RP2040, Blok, and Bit-C PRO :id=promicro_rp2040
Currently identical to [Adafruit KB2040](#kb2040).
+
+### STeMCell :id=stemcell
+
+Feature set currently identical to [Proton C](#proton_c).
+There are two versions of STeMCell available, with different pinouts:
+ - v1.0.0
+ - v2.0.0 (pre-release v1.0.1, v1.0.2)
+Default official firmware only supports v2.0.0 STeMCell.
+
+STeMCell has support to swap UART and I2C pins, to enable single-wire uart communication in STM chips.
+
+The following additional flags has to be used while compiling, based on the pin used for split communication.
+
+| Split Pin | Compile flags |
+|-----------|---------------|
+| D3 | -e STMC_US=yes|
+| D2 | Not needed |
+| D1 | -e STMC_IS=yes|
+| D0 | Not needed |
A platforms/chibios/boards/STEMCELL/board/board.mk => platforms/chibios/boards/STEMCELL/board/board.mk +15 -0
@@ 0,0 1,15 @@
+# Copyright 2022 Mega Mind (@megamind4089)
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Default pin config of nucleo64_411re has most pins in input pull up mode
+
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
+
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
A platforms/chibios/boards/STEMCELL/configs/board.h => platforms/chibios/boards/STEMCELL/configs/board.h +8 -0
@@ 0,0 1,8 @@
+// Copyright 2022 Mega Mind (@megamind4089)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include_next "board.h"
+
+#undef STM32_HSE_BYPASS
A platforms/chibios/boards/STEMCELL/configs/chconf.h => platforms/chibios/boards/STEMCELL/configs/chconf.h +9 -0
@@ 0,0 1,9 @@
+// Copyright 2022 Mega Mind (@megamind4089)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#define CH_CFG_ST_RESOLUTION 16
+#define CH_CFG_ST_FREQUENCY 10000
+
+#include_next <chconf.h>
A platforms/chibios/boards/STEMCELL/configs/config.h => platforms/chibios/boards/STEMCELL/configs/config.h +29 -0
@@ 0,0 1,29 @@
+// Copyright 2022 Mega Mind(@megamind4089)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
+
+/**======================
+ ** I2C Driver
+ *========================**/
+
+#if !defined(I2C1_SDA_PIN)
+# define I2C1_SDA_PIN D0
+#endif
+
+#if !defined(I2C1_SCL_PIN)
+# define I2C1_SCL_PIN D1
+#endif
+
+/**======================
+ ** SERIAL Driver
+ *========================**/
+
+#if !defined(SERIAL_USART_DRIVER)
+# define SERIAL_USART_DRIVER SD2
+#endif
+
A platforms/chibios/boards/STEMCELL/configs/halconf.h => platforms/chibios/boards/STEMCELL/configs/halconf.h +11 -0
@@ 0,0 1,11 @@
+// Copyright 2022 Mega Mind (@megamind4089)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#define PAL_USE_WAIT TRUE
+#define PAL_USE_CALLBACKS TRUE
+#define HAL_USE_I2C TRUE
+#define HAL_USE_SERIAL TRUE
+
+#include_next <halconf.h>
A platforms/chibios/boards/STEMCELL/configs/mcuconf.h => platforms/chibios/boards/STEMCELL/configs/mcuconf.h +231 -0
@@ 0,0 1,231 @@
+// Copyright 2022 Mega Mind (@megamind4089)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+#define STM32F411_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 4
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY 6
+#define STM32_IRQ_EXTI1_PRIORITY 6
+#define STM32_IRQ_EXTI2_PRIORITY 6
+#define STM32_IRQ_EXTI3_PRIORITY 6
+#define STM32_IRQ_EXTI4_PRIORITY 6
+#define STM32_IRQ_EXTI5_9_PRIORITY 6
+#define STM32_IRQ_EXTI10_15_PRIORITY 6
+#define STM32_IRQ_EXTI16_PRIORITY 6
+#define STM32_IRQ_EXTI17_PRIORITY 15
+#define STM32_IRQ_EXTI18_PRIORITY 6
+#define STM32_IRQ_EXTI19_PRIORITY 6
+#define STM32_IRQ_EXTI20_PRIORITY 6
+#define STM32_IRQ_EXTI21_PRIORITY 15
+#define STM32_IRQ_EXTI22_PRIORITY 15
+
+#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
+#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
+#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY 7
+#define STM32_IRQ_TIM2_PRIORITY 7
+#define STM32_IRQ_TIM3_PRIORITY 7
+#define STM32_IRQ_TIM4_PRIORITY 7
+#define STM32_IRQ_TIM5_PRIORITY 7
+
+#define STM32_IRQ_USART1_PRIORITY 12
+#define STM32_IRQ_USART2_PRIORITY 12
+#define STM32_IRQ_USART6_PRIORITY 12
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM10 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 TRUE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_USE_SPI3 FALSE
+#define STM32_I2S_SPI2_IRQ_PRIORITY 10
+#define STM32_I2S_SPI3_IRQ_PRIORITY 10
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI3_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_USE_TIM10 FALSE
+#define STM32_ICU_USE_TIM11 FALSE
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_USE_TIM10 FALSE
+#define STM32_PWM_USE_TIM11 FALSE
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 TRUE
+#define STM32_SERIAL_USE_USART2 TRUE
+#define STM32_SERIAL_USE_USART6 FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 TRUE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_HOST_WAKEUP_DURATION 2
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+#endif /* MCUCONF_H */
A platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h => platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h +57 -0
@@ 0,0 1,57 @@
+// Copyright 2022 Mega Mind (@megamind4089)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+// Pindefs for v2.0.0
+// https://megamind4089.github.io/STeMCell/pinout/
+
+// Left side (front)
+#ifdef STEMCELL_UART_SWAP
+# define D3 PAL_LINE(GPIOA, 3)
+# define D2 PAL_LINE(GPIOA, 2)
+#else
+# define D3 PAL_LINE(GPIOA, 2)
+# define D2 PAL_LINE(GPIOA, 3)
+#endif
+// GND
+// GND
+#ifdef STEMCELL_I2C_SWAP
+# define D1 PAL_LINE(GPIOB, 6)
+# define D0 PAL_LINE(GPIOB, 7)
+#else
+# define D1 PAL_LINE(GPIOB, 7)
+# define D0 PAL_LINE(GPIOB, 6)
+#endif
+
+#define D4 PAL_LINE(GPIOA, 15)
+#define C6 PAL_LINE(GPIOB, 3)
+#define D7 PAL_LINE(GPIOB, 4)
+#define E6 PAL_LINE(GPIOB, 5)
+#define B4 PAL_LINE(GPIOB, 8)
+#define B5 PAL_LINE(GPIOB, 9)
+
+// Right side (front)
+// RAW
+// GND
+// RESET
+// VCC
+#define F4 PAL_LINE(GPIOB, 10)
+#define F5 PAL_LINE(GPIOB, 2)
+#define F6 PAL_LINE(GPIOB, 1)
+#define F7 PAL_LINE(GPIOB, 0)
+
+#define B1 PAL_LINE(GPIOA, 5)
+#define B3 PAL_LINE(GPIOA, 6)
+#define B2 PAL_LINE(GPIOA, 7)
+#define B6 PAL_LINE(GPIOA, 4)
+
+// Extra elite-c compatible pinout
+#define B7 PAL_LINE(GPIOC, 13)
+#define D5 PAL_LINE(GPIOC, 14)
+#define C7 PAL_LINE(GPIOC, 15)
+#define F1 PAL_LINE(GPIOA, 0)
+#define F0 PAL_LINE(GPIOA, 1)
+
+// TX/RX pins of promicro
+#define B0 PAL_LINE(GPIOA, 9) // unconnected pin
A platforms/chibios/converters/promicro_to_stemcell/converter.mk => platforms/chibios/converters/promicro_to_stemcell/converter.mk +22 -0
@@ 0,0 1,22 @@
+# Copyright 2022 Mega Mind (@megamind4089)
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+MCU := STM32F411
+BOARD := STEMCELL
+BOOTLOADER := tinyuf2
+
+SERIAL_DRIVER ?= usart
+WS2812_DRIVER ?= bitbang
+
+EEPROM_DRIVER = wear_leveling
+WEAR_LEVELING_DRIVER = legacy
+
+
+ifeq ($(strip $(STMC_US)), yes)
+ OPT_DEFS += -DSTEMCELL_UART_SWAP
+endif
+
+ifeq ($(strip $(STMC_IS)), yes)
+ OPT_DEFS += -DSTEMCELL_I2C_SWAP
+endif
+