From fc0f266fab7866e540915be69b5ab559bfdc0318 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sat, 3 Dec 2022 18:29:18 +0100 Subject: [PATCH] fix(transport): correctly parse data and control bits --- src/transport/octets_to_sample.vhd | 68 +++++++++++++++++------------- 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/src/transport/octets_to_sample.vhd b/src/transport/octets_to_sample.vhd index 8c3990c..6319ca0 100644 --- a/src/transport/octets_to_sample.vhd +++ b/src/transport/octets_to_sample.vhd @@ -10,10 +10,10 @@ entity octets_to_samples is M : integer := 1; -- Number of converters S : integer := 1; -- Number of samples L : integer := 1; -- Number of lanes - F : integer := 16; -- Number of octets in a frame - CF : integer := 1; -- Number of control words + F : integer := 2; -- Number of octets in a frame + CF : integer := 0; -- Number of control words N : integer := 12; -- Size of a sample - Nn : integer := 32); -- Size of a word (sample + ctrl if CF + Nn : integer := 16); -- Size of a word (sample + ctrl if CF -- =0 port ( ci_char_clk : in std_logic; @@ -26,22 +26,24 @@ entity octets_to_samples is end entity octets_to_samples; architecture a1 of octets_to_samples is - constant CF_GROUP_COUNT : integer := CF; - constant CF_GROUP_LANES_COUNT : integer := L/CF; - constant CF_GROUP_CONVERTERS_COUNT : integer := M/CF; - signal samples_data : samples_array - (M - 1 downto 0, S - 1 downto 0) + (0 to M - 1, 0 to S - 1) (data(N - 1 downto 0), ctrl_bits(CS - 1 downto 0)); signal prev_samples_data : samples_array - (M - 1 downto 0, S - 1 downto 0) + (0 to M - 1, 0 to S - 1) + (data(N - 1 downto 0), ctrl_bits(CS - 1 downto 0)); + signal next_samples_data : samples_array + (0 to M - 1, 0 to S - 1) (data(N - 1 downto 0), ctrl_bits(CS - 1 downto 0)); signal reg_all_user_data : std_logic; -- if '0', set correct_data to '0'. + signal next_correct_data : std_logic; -- if '0', set correct_data to '0'. signal reg_error : std_logic; -- if err, repeat last samples. signal new_frame : std_logic; -- Whether current frame is new frame - signal reg_buffered_data : std_logic_vector(L*F-1 downto 0) := (others => '0'); + signal reg_buffered_data : std_logic_vector(L*F*8-1 downto 0) := (others => '0'); + signal current_buffered_data : std_logic_vector(L*F*8-1 downto 0) := (others => '0'); + signal buffered_data : std_logic_vector(L*F*8-1 downto 0) := (others => '0'); begin -- architecture a set_data: process (ci_char_clk, ci_reset) is @@ -51,57 +53,65 @@ begin -- architecture a reg_all_user_data <= '1'; reg_error <= '0'; reg_buffered_data <= (others => '0'); + next_correct_data <= '0'; elsif ci_char_clk'event and ci_char_clk = '1' then -- rising clock edge + if di_lanes_data(0).octet_index = 0 then + reg_all_user_data <= '1'; + end if; + do_samples_data <= next_samples_data; + co_correct_data <= next_correct_data; if new_frame = '1' then if reg_error = '1' then - do_samples_data <= prev_samples_data; + next_samples_data <= prev_samples_data; else - do_samples_data <= samples_data; + next_samples_data <= samples_data; prev_samples_data <= samples_data; end if; reg_buffered_data <= (others => '0'); - co_correct_data <= reg_all_user_data; + next_correct_data <= reg_all_user_data; reg_all_user_data <= '1'; reg_error <= '0'; + else + for i in 0 to L-1 loop + reg_buffered_data(L*F*8 - 1 - i*F*8 - 8*di_lanes_data(i).octet_index downto L*F*8 - 1 - i*F*8 - 8*di_lanes_data(i).octet_index - 7) <= di_lanes_data(i).d8b; + + if di_lanes_data(i).user_data = '0' or di_lanes_data(i).disparity_error = '1' or di_lanes_data(i).missing_error = '1' then + reg_all_user_data <= '0'; + end if; + end loop; -- i end if; - - for i in 0 to L-1 loop - reg_buffered_data(L*F - 1 - i*F - 8*di_lanes_data(i).octet_index downto L*F - 1 - i*F - 8*di_lanes_data(i).octet_index - 7) <= di_lanes_data(i).d8b; - - if di_lanes_data(i).user_data = '0' or di_lanes_data(i).disparity_error = '1' or di_lanes_data(i).missing_error = '1' then - reg_all_user_data <= '0'; - end if; - end loop; -- i end if; end process set_data; - new_frame <= '1' when di_lanes_data(0).octet_index = 0 else '0'; + new_frame <= '1' when di_lanes_data(0).octet_index = F - 1 else '0'; last_octet_data: for i in 0 to L-1 generate - reg_buffered_data(L*F - 1 - i*F - (F - 1)*8 downto L*F - 1 - i*F - (F - 1)*8 - 7) <= di_lanes_data(L - 1).d8b; + current_buffered_data(L*F*8 - 1 - i*F - (F - 1)*8 downto L*F*8 - 1 - i*F - (F - 1)*8 - 7) <= di_lanes_data(L - 1).d8b; end generate last_octet_data; + buffered_data <= current_buffered_data or reg_buffered_data; + multi_lane_no_cf: if CF = 0 generate converters: for ci in 0 to M - 1 generate samples: for si in 0 to S - 1 generate - samples_data(ci, si).data <= reg_buffered_data(L*F - 1 - ci*Nn*S - si*Nn downto L*F - 1 - ci*Nn*S - si*Nn - N + 1); + samples_data(ci, si).data <= buffered_data(L*F*8 - 1 - ci*Nn*S - si*Nn downto L*F*8 - 1 - ci*Nn*S - si*Nn - N + 1); control_bits: if CS > 0 generate - samples_data(ci, si).ctrl_bits <= reg_buffered_data(L*F - 1 - ci*Nn*S - si*Nn - si*N downto L*F - 1 - ci*Nn*S - si*Nn - si*N - CS + 1); + samples_data(ci, si).ctrl_bits <= buffered_data(L*F*8 - 1 - ci*Nn*S - si*Nn - N downto L*F*8 - 1 - ci*Nn*S - si*Nn - N - CS + 1); end generate control_bits; end generate samples; end generate converters; end generate multi_lane_no_cf; multi_lane_cf: if CF > 0 generate - cf_groups: for cfi in 0 to CF_GROUP_COUNT-1 generate - converters: for ci in 0 to CF_GROUP_CONVERTERS_COUNT-1 generate + cf_groups: for cfi in 0 to CF-1 generate + converters: for ci in 0 to M/CF-1 generate samples: for si in 0 to S - 1 generate - samples_data(ci + cfi*CF_GROUP_CONVERTERS_COUNT, si).data <= reg_buffered_data(L*F - 1 - F*CF_GROUP_LANES_COUNT - ci*Nn*S - si*Nn downto L*F - 1 - F*CF_GROUP_LANES_COUNT - ci*Nn*S - si*Nn - N + 1); + samples_data(ci + cfi*M/CF, si).data <= buffered_data(L*F*8 - 1 - cfi*F*8*L/CF - ci*Nn*S - si*Nn downto L*F*8 - 1 - cfi*F*8*L/CF - ci*Nn*S - si*Nn - N + 1); control_bits: if CS > 0 generate - samples_data(ci + cfi*CF_GROUP_CONVERTERS_COUNT, si).ctrl_bits <= reg_buffered_data(L*F - 1 - F*CF_GROUP_LANES_COUNT - (M-1)*Nn*S - ci*S*CS - si*CS downto L*F - 1 - F*CF_GROUP_LANES_COUNT - (M-1)*Nn*S - ci*S*CS - si*CS - CS + 1); + samples_data(ci + cfi*M/CF, si).ctrl_bits <= buffered_data(L*F*8 - 1 - cfi*F*8*L/CF - (M/CF)*S*Nn - ci*S*CS - si*CS downto L*F*8 - 1 - cfi*F*8*L/CF - (M/CF)*Nn*S - ci*S*CS - si*CS - CS + 1); end generate control_bits; end generate samples; end generate converters; -- 2.48.1