From f06b8ffb364d23a244737dbbed8f925eafb719da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sun, 4 Dec 2022 20:57:34 +0100 Subject: [PATCH] chore: add Quartus project with configured testbenches --- c5_pin_model_dump.txt | 120 +++++++++++++++++++++++++ jesd204b_rx.qpf | 31 +++++++ jesd204b_rx.qsf | 125 ++++++++++++++++++++++++++ jesd204b_rx_description.txt | 0 jesd204b_rx_nativelink_simulation.rpt | 24 +++++ testbench/descrambler_tb.vhd | 34 +++++++ 6 files changed, 334 insertions(+) create mode 100644 c5_pin_model_dump.txt create mode 100644 jesd204b_rx.qpf create mode 100644 jesd204b_rx.qsf create mode 100644 jesd204b_rx_description.txt create mode 100644 jesd204b_rx_nativelink_simulation.rpt create mode 100644 testbench/descrambler_tb.vhd diff --git a/c5_pin_model_dump.txt b/c5_pin_model_dump.txt new file mode 100644 index 0000000..b7bf0f1 --- /dev/null +++ b/c5_pin_model_dump.txt @@ -0,0 +1,120 @@ +io_4iomodule_c5_index: 77gpio_index: 2 +io_4iomodule_c5_index: 60gpio_index: 476 +io_4iomodule_c5_index: 62gpio_index: 6 +io_4iomodule_c5_index: 26gpio_index: 472 +io_4iomodule_c5_index: 20gpio_index: 10 +io_4iomodule_c5_index: 12gpio_index: 468 +io_4iomodule_c5_index: 27gpio_index: 14 +io_4iomodule_c5_index: 71gpio_index: 464 +io_4iomodule_c5_index: 56gpio_index: 19 +io_4iomodule_c5_index: 14gpio_index: 460 +io_4iomodule_c5_index: 22gpio_index: 22 +io_4iomodule_c5_index: 10gpio_index: 456 +io_4iomodule_c5_index: 11gpio_index: 27 +io_4iomodule_c5_index: 73gpio_index: 452 +io_4iomodule_c5_index: 74gpio_index: 30 +io_4iomodule_c5_index: 76gpio_index: 448 +io_4iomodule_c5_index: 2gpio_index: 35 +io_4iomodule_c5_index: 78gpio_index: 444 +io_4iomodule_c5_index: 9gpio_index: 38 +io_4iomodule_c5_index: 36gpio_index: 440 +io_4iomodule_c5_index: 51gpio_index: 43 +io_4iomodule_c5_index: 23gpio_index: 436 +io_4iomodule_c5_index: 53gpio_index: 46 +io_4iomodule_c5_index: 50gpio_index: 432 +io_4iomodule_c5_index: 0gpio_index: 51 +io_4iomodule_c5_index: 43gpio_index: 428 +io_4iomodule_c5_index: 67gpio_index: 54 +io_4iomodule_c5_index: 16gpio_index: 424 +io_4iomodule_c5_index: 44gpio_index: 59 +io_4iomodule_c5_index: 29gpio_index: 420 +io_4iomodule_c5_index: 1gpio_index: 62 +io_4iomodule_c5_index: 8gpio_index: 416 +io_4iomodule_c5_index: 65gpio_index: 67 +io_4iomodule_c5_index: 25gpio_index: 412 +io_4iomodule_c5_index: 40gpio_index: 70 +io_4iomodule_c5_index: 55gpio_index: 408 +io_4iomodule_c5_index: 66gpio_index: 75 +io_4iomodule_c5_index: 5gpio_index: 404 +io_4iomodule_c5_index: 61gpio_index: 78 +io_4iomodule_c5_index: 17gpio_index: 400 +io_4iomodule_c5_index: 42gpio_index: 83 +io_4iomodule_c5_index: 59gpio_index: 396 +io_4iomodule_c5_index: 54gpio_index: 86 +io_4iomodule_c5_index: 58gpio_index: 392 +io_4iomodule_c5_index: 33gpio_index: 91 +io_4iomodule_c5_index: 41gpio_index: 388 +io_4iomodule_c5_index: 69gpio_index: 94 +io_4iomodule_c5_index: 3gpio_index: 384 +io_4iomodule_c5_index: 18gpio_index: 99 +io_4iomodule_c5_index: 15gpio_index: 380 +io_4iomodule_c5_index: 6gpio_index: 102 +io_4iomodule_c5_index: 7gpio_index: 376 +io_4iomodule_c5_index: 47gpio_index: 107 +io_4iomodule_c5_index: 39gpio_index: 372 +io_4iomodule_c5_index: 32gpio_index: 110 +io_4iomodule_c5_index: 24gpio_index: 368 +io_4iomodule_c5_index: 48gpio_index: 115 +io_4iomodule_c5_index: 57gpio_index: 364 +io_4iomodule_c5_index: 64gpio_index: 118 +io_4iomodule_c5_index: 31gpio_index: 360 +io_4iomodule_c5_index: 46gpio_index: 123 +io_4iomodule_c5_index: 21gpio_index: 356 +io_4iomodule_c5_index: 72gpio_index: 126 +io_4iomodule_c5_index: 70gpio_index: 352 +io_4iomodule_c5_index: 49gpio_index: 131 +io_4iomodule_c5_index: 63gpio_index: 348 +io_4iomodule_c5_index: 79gpio_index: 134 +io_4iomodule_c5_index: 28gpio_index: 344 +io_4iomodule_c5_index: 34gpio_index: 139 +io_4iomodule_c5_index: 4gpio_index: 340 +io_4iomodule_c5_index: 68gpio_index: 142 +io_4iomodule_c5_index: 37gpio_index: 336 +io_4iomodule_c5_index: 45gpio_index: 147 +io_4iomodule_c5_index: 35gpio_index: 332 +io_4iomodule_c5_index: 38gpio_index: 150 +io_4iomodule_c5_index: 19gpio_index: 328 +io_4iomodule_c5_index: 52gpio_index: 155 +io_4iomodule_c5_index: 30gpio_index: 324 +io_4iomodule_c5_index: 75gpio_index: 158 +io_4iomodule_c5_index: 13gpio_index: 320 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 15gpio_index: 165 +io_4iomodule_h_c5_index: 27gpio_index: 169 +io_4iomodule_h_c5_index: 30gpio_index: 173 +io_4iomodule_h_c5_index: 36gpio_index: 176 +io_4iomodule_h_c5_index: 37gpio_index: 180 +io_4iomodule_h_c5_index: 26gpio_index: 184 +io_4iomodule_h_c5_index: 24gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 21gpio_index: 196 +io_4iomodule_h_c5_index: 18gpio_index: 200 +io_4iomodule_h_c5_index: 6gpio_index: 204 +io_4iomodule_h_c5_index: 31gpio_index: 208 +io_4iomodule_h_c5_index: 3gpio_index: 212 +io_4iomodule_h_c5_index: 20gpio_index: 216 +io_4iomodule_h_c5_index: 4gpio_index: 220 +io_4iomodule_h_c5_index: 29gpio_index: 224 +io_4iomodule_h_c5_index: 22gpio_index: 228 +io_4iomodule_h_c5_index: 16gpio_index: 232 +io_4iomodule_h_c5_index: 9gpio_index: 236 +io_4iomodule_h_c5_index: 25gpio_index: 240 +io_4iomodule_h_c5_index: 11gpio_index: 244 +io_4iomodule_h_c5_index: 19gpio_index: 248 +io_4iomodule_h_c5_index: 23gpio_index: 252 +io_4iomodule_h_c5_index: 17gpio_index: 256 +io_4iomodule_h_c5_index: 8gpio_index: 260 +io_4iomodule_h_c5_index: 38gpio_index: 264 +io_4iomodule_h_c5_index: 2gpio_index: 268 +io_4iomodule_h_c5_index: 12gpio_index: 272 +io_4iomodule_h_c5_index: 35gpio_index: 276 +io_4iomodule_h_c5_index: 13gpio_index: 280 +io_4iomodule_h_c5_index: 5gpio_index: 284 +io_4iomodule_h_c5_index: 28gpio_index: 288 +io_4iomodule_h_c5_index: 7gpio_index: 292 +io_4iomodule_h_c5_index: 34gpio_index: 296 +io_4iomodule_h_c5_index: 14gpio_index: 300 +io_4iomodule_h_c5_index: 33gpio_index: 304 +io_4iomodule_h_c5_index: 39gpio_index: 308 +io_4iomodule_h_c5_index: 32gpio_index: 312 +io_4iomodule_h_c5_index: 10gpio_index: 316 diff --git a/jesd204b_rx.qpf b/jesd204b_rx.qpf new file mode 100644 index 0000000..3ba95dc --- /dev/null +++ b/jesd204b_rx.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2021 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition +# Date created = 18:31:58 December 04, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "21.1" +DATE = "18:31:58 December 04, 2022" + +# Revisions + +PROJECT_REVISION = "jesd204b_rx" diff --git a/jesd204b_rx.qsf b/jesd204b_rx.qsf new file mode 100644 index 0000000..e7aaee9 --- /dev/null +++ b/jesd204b_rx.qsf @@ -0,0 +1,125 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2021 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition +# Date created = 18:31:58 December 04, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# jesd204b_rx_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC7D6F31I7 +set_global_assignment -name TOP_LEVEL_ENTITY frame_alignment +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:31:58 DECEMBER 04, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH lane_alignment_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME char_alignment -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id char_alignment +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id char_alignment +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME char_alignment_tb -section_id char_alignment +set_global_assignment -name EDA_TEST_BENCH_NAME ilas_parser_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ilas_parser_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id ilas_parser_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ilas_parser_tb -section_id ilas_parser_tb +set_global_assignment -name EDA_TEST_BENCH_NAME link_controller_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id link_controller_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id link_controller_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME link_controller_tb -section_id link_controller_tb +set_global_assignment -name EDA_TEST_BENCH_NAME an8b10bdecoder_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id an8b10bdecoder_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id an8b10bdecoder_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME an8b10bdecoder_tb -section_id an8b10bdecoder_tb +set_global_assignment -name EDA_TEST_BENCH_NAME lane_alignment_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id lane_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id lane_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME lane_alignment_tb -section_id lane_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_NAME frame_alignment_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id frame_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id frame_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME frame_alignment_tb -section_id frame_alignment_tb +set_global_assignment -name VHDL_FILE testbench/data_link/an8b10bdecoder_tb.vhd +set_global_assignment -name VHDL_FILE src/data_link/an8b10b_decoder.vhd +set_global_assignment -name VHDL_FILE testbench/data_link/link_controller_tb.vhd +set_global_assignment -name VHDL_FILE testbench/data_link/lane_alignment_tb.vhd +set_global_assignment -name VHDL_FILE testbench/data_link/ilas_parser_tb.vhd +set_global_assignment -name VHDL_FILE testbench/data_link/functions.vhd +set_global_assignment -name VHDL_FILE testbench/data_link/frame_alignment_tb.vhd +set_global_assignment -name VHDL_FILE testbench/data_link/char_alignment_tb.vhd +set_global_assignment -name VHDL_FILE src/data_link/link_controller.vhd +set_global_assignment -name VHDL_FILE src/data_link/lane_alignment.vhd +set_global_assignment -name VHDL_FILE src/data_link/ilas_parser.vhd +set_global_assignment -name VHDL_FILE src/data_link/frame_alignment.vhd +set_global_assignment -name VHDL_FILE src/data_link/error_handler.vhd +set_global_assignment -name VHDL_FILE src/data_link/data_link_pkg.vhd +set_global_assignment -name VHDL_FILE src/data_link/data_link_layer.vhd +set_global_assignment -name VHDL_FILE src/data_link/char_alignment.vhd +set_global_assignment -name VHDL_FILE src/descrambler.vhd +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id char_alignment +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/char_alignment_tb.vhd -section_id char_alignment +set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/ilas_parser.vhd -section_id ilas_parser_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id ilas_parser_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/ilas_parser_tb.vhd -section_id ilas_parser_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id link_controller_tb +set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/ilas_parser.vhd -section_id link_controller_tb +set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/link_controller.vhd -section_id link_controller_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/link_controller_tb.vhd -section_id link_controller_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id an8b10bdecoder_tb +set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/an8b10b_decoder.vhd -section_id an8b10bdecoder_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/an8b10bdecoder_tb.vhd -section_id an8b10bdecoder_tb +set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/lane_alignment.vhd -section_id lane_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id lane_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/lane_alignment_tb.vhd -section_id lane_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/frame_alignment.vhd -section_id frame_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id frame_alignment_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/frame_alignment_tb.vhd -section_id frame_alignment_tb \ No newline at end of file diff --git a/jesd204b_rx_description.txt b/jesd204b_rx_description.txt new file mode 100644 index 0000000..e69de29 diff --git a/jesd204b_rx_nativelink_simulation.rpt b/jesd204b_rx_nativelink_simulation.rpt new file mode 100644 index 0000000..dd09c25 --- /dev/null +++ b/jesd204b_rx_nativelink_simulation.rpt @@ -0,0 +1,24 @@ +Info: Start Nativelink Simulation process +Info: NativeLink has detected VHDL design -- VHDL simulation models will be used + +========= EDA Simulation Settings ===================== + +Sim Mode : RTL +Family : cyclonev +Quartus root : /home/Documents/Linux/intelFPGA/21.1/quartus/linux64/ +Quartus sim root : /home/Documents/Linux/intelFPGA/21.1/quartus/eda/sim_lib +Simulation Tool : questa intel fpga +Simulation Language : vhdl +Version : 93 +Simulation Mode : GUI +Sim Output File : +Sim SDF file : +Sim dir : simulation/modelsim + +======================================================= + +Info: Starting NativeLink simulation with Questa Intel FPGA software +Sourced NativeLink script /home/Documents/Linux/intelFPGA/21.1/quartus/common/tcl/internal/nativelink/modelsim.tcl +Warning: File jesd204b_rx_run_msim_rtl_vhdl.do already exists - backing up current file as jesd204b_rx_run_msim_rtl_vhdl.do.bak11 +Info: Spawning Questa Intel FPGA Simulation software +Info: NativeLink simulation flow was successful diff --git a/testbench/descrambler_tb.vhd b/testbench/descrambler_tb.vhd new file mode 100644 index 0000000..48a7568 --- /dev/null +++ b/testbench/descrambler_tb.vhd @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.testing_functions.all; +use work.data_link_pkg.all; + +entity descrambler_tb is +end entity descrambler_tb; + +architecture a1 of descrambler_tb is + constant clk_period : time := 1 ns; -- The clock period + + signal clk : std_logic := '0'; -- The clock + signal reset : std_logic := '0'; -- The reset + + signal di_char : frame_character; + signal do_char : frame_character; + +begin -- architecture a1 + uut: entity work.descrambler + port map ( + di_char => di_char, + do_char => do_char, + ci_reset => reset, + ci_char_clk => clk + ); + + clk <= not clk after clk_period/2; + reset <= '1' after clk_period*2; + + test: process is + begin -- process test + wait for 200 ms; + end process test; +end architecture a1; -- 2.48.1