From ed3bb98ce9380a956f6d769d6116d9ab28975dda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Fri, 2 Dec 2022 20:13:35 +0100 Subject: [PATCH] feat(transport): add transport layer entity --- src/transport/transport_layer.vhd | 42 +++++++++++++++++++++++++++++++ src/transport/transport_pkg.vhd | 15 +++++++++++ 2 files changed, 57 insertions(+) create mode 100644 src/transport/transport_layer.vhd create mode 100644 src/transport/transport_pkg.vhd diff --git a/src/transport/transport_layer.vhd b/src/transport/transport_layer.vhd new file mode 100644 index 0000000..0aa3890 --- /dev/null +++ b/src/transport/transport_layer.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.data_link_pkg.all; +use work.transport_pkg.all; + +entity transport_layer is + generic ( + M : integer := 1; -- Count of converters + S : integer := 1; -- Count of samples + L : integer := 1); -- Count of lanes + port ( + ci_char_clk : in std_logic; + ci_frame_clk : in std_logic; + ci_reset : in std_logic; + di_lanes_data : in frame_character_array(L - 1 downto 0); + + ci_N : in integer range 0 to 256; -- Number of bits per sample + ci_Nn : in integer range 0 to 256; -- Number of bits per sample + control + -- bits + co_correct_data : out std_logic; + do_samples_data : out samples_array(M - 1 downto 0, S - 1 downto 0)); +end entity transport_layer; + +architecture a1 of transport_layer is + +begin -- architecture a1 + + octets_to_samples: entity work.octets_to_samples + generic map ( + M => M, + S => S, + L => L) + port map ( + ci_char_clk => ci_char_clk, + ci_frame_clk => ci_frame_clk, + di_lanes_data => di_lanes_data, + ci_N => ci_N, + ci_Nn => ci_Nn, + co_correct_data => co_correct_data, + do_samples_data => do_samples_data); + +end architecture a1; diff --git a/src/transport/transport_pkg.vhd b/src/transport/transport_pkg.vhd new file mode 100644 index 0000000..303b912 --- /dev/null +++ b/src/transport/transport_pkg.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.data_link_pkg.all; + +package transport_pkg is + + type sample is record + data : std_logic_vector;--(SAMPLE_SIZE - 1 downto 0); + ctrl_bits : std_logic_vector;--(CONTROL_SIZE - 1 downto 0); + end record sample; + + type frame_character_array is array (natural range <>) of frame_character; + type samples_array is array (natural range <>, natural range <>) of sample; + +end package transport_pkg; -- 2.48.1