From ebd83e823d98495b72b958dcc87b5a56ab9c91b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sat, 1 Apr 2023 17:20:18 +0200 Subject: [PATCH] tests: adjust tests for new changes --- testbench/data_link/lane_alignment_tb.vhd | 14 +++++++------- testbench/data_link/link_controller_tb.vhd | 22 +++++++++++++--------- testbench/jesd204b_rx_data_tb.vhd | 3 +-- testbench/jesd204b_rx_ils_tb.vhd | 3 +-- testbench/jesd204b_rx_kchars_tb.vhd | 3 +-- 5 files changed, 23 insertions(+), 22 deletions(-) diff --git a/testbench/data_link/lane_alignment_tb.vhd b/testbench/data_link/lane_alignment_tb.vhd index d5add9d..e42762d 100644 --- a/testbench/data_link/lane_alignment_tb.vhd +++ b/testbench/data_link/lane_alignment_tb.vhd @@ -28,19 +28,19 @@ architecture a1 of lane_alignment_tb is (CGS, '0', ('1', '0', '0', "10111100", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), (CGS, '0', ('1', '0', '0', "10111100", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), (CGS, '0', ('1', '0', '0', "10111100", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), - (ILS, '0', ('1', '0', '0', "01111100", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), + (ILS, '0', ('1', '0', '0', "00011100", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), (ILS, '0', ('0', '0', '0', "00000000", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), (ILS, '0', ('0', '0', '0', "00000001", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), (ILS, '0', ('0', '0', '0', "00000010", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), - (DATA, '1', ('0', '0', '0', "00000011", '0'), ('1', '0', '0', "01111100", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00000011", '0'), ('1', '0', '0', "00011100", '0'), '1', '1', '0'), (DATA, '1', ('0', '0', '0', "00000100", '0'), ('0', '0', '0', "00000000", '0'), '1', '1', '0'), (DATA, '1', ('0', '0', '0', "00000101", '0'), ('0', '0', '0', "00000001", '0'), '1', '1', '0'), (DATA, '1', ('0', '0', '0', "00000110", '0'), ('0', '0', '0', "00000010", '0'), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00000111", '0'), ('0', '0', '0', "00000011", '0'), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001000", '0'), ('0', '0', '0', "00000100", '0'), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001001", '0'), ('0', '0', '0', "00000101", '0'), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001010", '0'), ('0', '0', '0', "00000110", '0'), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001011", '0'), ('0', '0', '0', "00000111", '0'), '1', '1', '0') + (DATA, '1', ('0', '0', '0', "00000111", '0'), ('0', '0', '0', "00000011", '1'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001000", '0'), ('0', '0', '0', "00000100", '1'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001001", '0'), ('0', '0', '0', "00000101", '1'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001010", '0'), ('0', '0', '0', "00000110", '1'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001011", '0'), ('0', '0', '0', "00000111", '1'), '1', '1', '0') ); constant clk_period : time := 1 ns; diff --git a/testbench/data_link/link_controller_tb.vhd b/testbench/data_link/link_controller_tb.vhd index 25c3eee..bc2663a 100644 --- a/testbench/data_link/link_controller_tb.vhd +++ b/testbench/data_link/link_controller_tb.vhd @@ -89,7 +89,7 @@ architecture a1 of link_controller_tb is (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '1', CGS, '0', '0', -1), + (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), (('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --R (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), @@ -106,6 +106,7 @@ architecture a1 of link_controller_tb is (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), (('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --A (('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --R (('1', '0', '0', "10011100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), @@ -123,6 +124,7 @@ architecture a1 of link_controller_tb is (('0', '0', '0', "11111111", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), (('0', '0', '0', "00110000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00110000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), (('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --A (('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --R (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), @@ -140,6 +142,7 @@ architecture a1 of link_controller_tb is (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), (('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --A (('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --R (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), @@ -157,7 +160,8 @@ architecture a1 of link_controller_tb is (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --A + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), + (('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), --A (('0', '0', '0', "01010101", '0'), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), (('0', '0', '0', "01010101", '0'), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), (('0', '0', '0', "01010101", '0'), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), @@ -167,7 +171,7 @@ architecture a1 of link_controller_tb is (('0', '0', '0', "01010101", '0'), '0', '1', '0', '0', '0', '0', '1', DATA, '0', '1', 0), (('0', '0', '0', "01010101", '0'), '0', '1', '0', '0', '1', '0', '1', DATA, '0', '1', 0), (('0', '0', '0', "01010101", '0'), '0', '0', '0', '0', '1', '0', '1', DATA, '0', '1', 0), - (('0', '0', '0', "01010101", '0'), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), + (('0', '0', '0', "01010101", '0'), '1', '0', '0', '0', '0', '0', '1', INIT, '0', '0', -1), (('0', '0', '0', "01010101", '0'), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), (('0', '0', '0', "01010101", '0'), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), @@ -177,9 +181,9 @@ architecture a1 of link_controller_tb is (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), + (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '1', CGS, '0', '0', -1), - (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '1', CGS, '0', '0', -1), - (('0', '0', '0', "00000000", '0'), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '1', '0', '0', '0', '0', '0', '1', INIT, '0', '0', -1), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), @@ -187,12 +191,12 @@ architecture a1 of link_controller_tb is (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1) ); + constant F : integer range 0 to 256 := 2; + constant K : integer range 0 to 32 := 9; + constant char_clk_period : time := 1 ns; constant frame_clk_period : time := char_clk_period * F; - constant F : integer range 0 to 256 := 17; - constant K : integer range 0 to 32 := 1; - signal char_clk : std_logic := '0'; signal frame_clk : std_logic := '0'; signal reset : std_logic := '0'; @@ -247,7 +251,7 @@ begin -- architecture a1 frame_clk_gen: process is begin -- process clk_gen wait for frame_clk_period/2; - frame_clk <= not clk; + frame_clk <= not frame_clk; end process frame_clk_gen; reset_gen: process is diff --git a/testbench/jesd204b_rx_data_tb.vhd b/testbench/jesd204b_rx_data_tb.vhd index 3c0d2be..6eb176a 100644 --- a/testbench/jesd204b_rx_data_tb.vhd +++ b/testbench/jesd204b_rx_data_tb.vhd @@ -139,7 +139,6 @@ architecture a1 of jesd204b_rx_data_tb is signal test_vec_index : integer := 0; - signal co_lane_config : link_config; signal co_nsynced : std_logic; signal co_error : std_logic; signal do_samples : samples_array (M-1 downto 0, S-1 downto 0) @@ -162,8 +161,8 @@ begin -- architecture a1 ci_char_clk => char_clk, ci_frame_clk => frame_clk, ci_reset => reset, + ci_request_sync => '0', di_transceiver_data => di_transceiver_data, - co_lane_config => co_lane_config, co_nsynced => co_nsynced, co_error => co_error, do_samples => do_samples, diff --git a/testbench/jesd204b_rx_ils_tb.vhd b/testbench/jesd204b_rx_ils_tb.vhd index 15524c8..0605137 100644 --- a/testbench/jesd204b_rx_ils_tb.vhd +++ b/testbench/jesd204b_rx_ils_tb.vhd @@ -135,7 +135,6 @@ architecture a1 of jesd204b_rx_ils_tb is signal test_vec_index : integer := 0; - signal co_lane_config : link_config; signal co_nsynced : std_logic; signal co_error : std_logic; signal do_samples : samples_array (M-1 downto 0, S-1 downto 0) @@ -158,8 +157,8 @@ begin -- architecture a1 ci_char_clk => char_clk, ci_frame_clk => frame_clk, ci_reset => reset, + ci_request_sync => '0', di_transceiver_data => di_transceiver_data, - co_lane_config => co_lane_config, co_nsynced => co_nsynced, co_error => co_error, do_samples => do_samples, diff --git a/testbench/jesd204b_rx_kchars_tb.vhd b/testbench/jesd204b_rx_kchars_tb.vhd index ef93732..f0cb8c3 100644 --- a/testbench/jesd204b_rx_kchars_tb.vhd +++ b/testbench/jesd204b_rx_kchars_tb.vhd @@ -75,7 +75,6 @@ architecture a1 of jesd204b_rx_kchars_tb is signal test_vec_index : integer := 0; - signal co_lane_config : link_config; signal co_nsynced : std_logic; signal co_error : std_logic; signal do_samples : samples_array (M-1 downto 0, S-1 downto 0) @@ -98,8 +97,8 @@ begin -- architecture a1 ci_char_clk => char_clk, ci_frame_clk => frame_clk, ci_reset => reset, + ci_request_sync => '0', di_transceiver_data => di_transceiver_data, - co_lane_config => co_lane_config, co_nsynced => co_nsynced, co_error => co_error, do_samples => do_samples, -- 2.48.1