From e3ba91e302b52d73b2047e121fd42e6e63096179 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sun, 4 Dec 2022 20:54:35 +0100 Subject: [PATCH] fix(link): make testbenches work in quartus, fix old testbenches --- ...{8b10b_decoder.vhd => an8b10b_decoder.vhd} | 0 src/data_link/data_link_layer.vhd | 27 +- src/data_link/ilas_parser.vhd | 11 +- src/data_link/lane_alignment.vhd | 2 +- src/jesd204b_rx.vhd | 9 +- ...0bdecoder_tb.vhd => an8b10bdecoder_tb.vhd} | 15 +- testbench/data_link/char_alignment_tb.vhd | 13 +- testbench/data_link/frame_alignment_tb.vhd | 21 +- testbench/data_link/ilas_parser_tb.vhd | 303 +++++++++--------- testbench/data_link/lane_alignment_tb.vhd | 56 ++-- testbench/data_link/link_controller_tb.vhd | 219 +++++++------ 11 files changed, 369 insertions(+), 307 deletions(-) rename src/data_link/{8b10b_decoder.vhd => an8b10b_decoder.vhd} (100%) rename testbench/data_link/{8b10bdecoder_tb.vhd => an8b10bdecoder_tb.vhd} (92%) diff --git a/src/data_link/8b10b_decoder.vhd b/src/data_link/an8b10b_decoder.vhd similarity index 100% rename from src/data_link/8b10b_decoder.vhd rename to src/data_link/an8b10b_decoder.vhd diff --git a/src/data_link/data_link_layer.vhd b/src/data_link/data_link_layer.vhd index 1859755..2037a6d 100644 --- a/src/data_link/data_link_layer.vhd +++ b/src/data_link/data_link_layer.vhd @@ -7,15 +7,16 @@ entity data_link_layer is K_character : std_logic_vector(7 downto 0) := "10111100"; R_character : std_logic_vector(7 downto 0) := "00011100"; A_character : std_logic_vector(7 downto 0) := "01111100"; - Q_character : std_logic_vector(7 downto 0) := "10011100"); + Q_character : std_logic_vector(7 downto 0) := "10011100"; + ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5); + SCRAMBLING : std_logic := '0'; + F : integer := 2; + K : integer := 1); port ( ci_char_clk : in std_logic; ci_reset : in std_logic; - -- lane configuration - ci_F : in integer range 0 to 256; - ci_K : in integer range 0 to 32; - ci_scrambled : in std_logic; + -- link configuration do_lane_config : out link_config; -- synchronization @@ -74,7 +75,7 @@ begin -- architecture a1 ci_char_clk => ci_char_clk, ci_reset => ci_reset, ci_state => link_controller_co_state, - ci_F => ci_F, + ci_F => F, di_char => decoder_do_char, ci_config => ci_error_config, ci_lane_alignment_error => lane_alignment_co_error, @@ -91,8 +92,8 @@ begin -- architecture a1 ci_char_clk => ci_char_clk, ci_reset => ci_reset, ci_resync => link_controller_ci_resync, - ci_F => ci_F, - ci_K => ci_K, + ci_F => F, + ci_K => K, ci_lane_alignment_error => lane_alignment_co_error, ci_lane_alignment_aligned => lane_alignment_co_aligned, ci_lane_alignment_ready => lane_alignment_co_ready, @@ -123,8 +124,8 @@ begin -- architecture a1 port map ( ci_char_clk => ci_char_clk, ci_reset => ci_reset, - ci_F => ci_F, - ci_K => ci_K, + ci_F => F, + ci_K => K, ci_state => link_controller_co_state, ci_realign => lane_alignment_ci_realign, co_ready => lane_alignment_co_ready, @@ -138,9 +139,9 @@ begin -- architecture a1 port map ( ci_char_clk => ci_char_clk, ci_reset => ci_reset, - ci_scrambled => ci_scrambled, - ci_F => ci_F, - ci_K => ci_K, + ci_scrambled => SCRAMBLING, + ci_F => F, + ci_K => K, co_correct_sync_chars => frame_alignment_co_correct_sync_chars, ci_request_sync => frame_alignment_ci_request_sync, ci_realign => frame_alignment_ci_realign, diff --git a/src/data_link/ilas_parser.vhd b/src/data_link/ilas_parser.vhd index e1efa8e..1f570d3 100644 --- a/src/data_link/ilas_parser.vhd +++ b/src/data_link/ilas_parser.vhd @@ -102,7 +102,7 @@ begin -- architecture a1 end process set_next; check_chars: process (ci_char_clk, ci_reset) is - variable up_index : integer; + variable up_index : integer range 7 to link_config_length-1; variable processing_ilas : std_logic; begin -- process check_chars processing_ilas := next_processing_ilas or reg_processing_ilas; @@ -121,7 +121,12 @@ begin -- architecture a1 link_config_data <= (others => '0'); finished <= '0'; end if; - elsif err = '1' then + elsif ci_char_clk'event and ci_char_clk = '1' and err = '1' then + if next_processing_ilas = '0' then + err <= '0'; + co_unexpected_char <= '0'; + co_wrong_chksum <= '0'; + end if; -- If there is an error, stop processing. elsif ci_char_clk'event and ci_char_clk = '1' and processing_ilas = '1' then -- rising clock edge if reg_octet_index = 0 then -- Should be /R/ @@ -178,7 +183,7 @@ begin -- architecture a1 next_multiframe_index <= 0 when reg_processing_ilas = '0' and next_processing_ilas = '0' else (reg_multiframe_index + 1) when reg_octet_index = octets_in_multiframe - 1 else reg_multiframe_index; - next_octet_index <= 0 when next_processing_ilas = '0' and reg_processing_ilas = '0' else + next_octet_index <= 0 when (next_processing_ilas = '0' and reg_processing_ilas = '0') or (next_processing_ilas = '0' and reg_processing_ilas = '1') else (reg_octet_index + 1) mod octets_in_multiframe; -- config diff --git a/src/data_link/lane_alignment.vhd b/src/data_link/lane_alignment.vhd index 54cb94d..87a8a90 100644 --- a/src/data_link/lane_alignment.vhd +++ b/src/data_link/lane_alignment.vhd @@ -84,6 +84,6 @@ begin -- architecture a1 do_char <= dummy_character when ci_state = INIT or reg_started = '0' else buff(reg_read_index); - do_char.user_data <= '1' when ci_state = DATA and reg_started = '1' else '0'; + -- TODO do_char.user_data <= '1' when ci_state = DATA and reg_started = '1' else '0'; end architecture a1; diff --git a/src/jesd204b_rx.vhd b/src/jesd204b_rx.vhd index 2f0e24e..933a7f5 100644 --- a/src/jesd204b_rx.vhd +++ b/src/jesd204b_rx.vhd @@ -89,13 +89,14 @@ begin -- architecture a1 K_character => K_character, R_character => R_character, A_character => A_character, - Q_character => Q_character) + Q_character => Q_character, + ERROR_CONFIG => ERROR_CONFIG, + SCRAMBLING => SCRAMBLING, + F => F, + K => K) port map ( ci_char_clk => ci_char_clk, ci_reset => ci_reset, - ci_F => F, - ci_K => K, - ci_scrambled => SCRAMBLING, do_lane_config => lane_configuration_array(i), co_lane_ready => data_link_ready_vector(i), ci_lane_start => data_link_start, diff --git a/testbench/data_link/8b10bdecoder_tb.vhd b/testbench/data_link/an8b10bdecoder_tb.vhd similarity index 92% rename from testbench/data_link/8b10bdecoder_tb.vhd rename to testbench/data_link/an8b10bdecoder_tb.vhd index d94942f..99c10e8 100644 --- a/testbench/data_link/8b10bdecoder_tb.vhd +++ b/testbench/data_link/an8b10bdecoder_tb.vhd @@ -50,7 +50,7 @@ architecture a1 of an8b10bdecoder_tb is signal co_missing_error : std_logic; signal co_disparity_error : std_logic; - signal char : character_vector := ('0', '0', '0', "00000000"); + signal char : character_vector := ('0', '0', '0', "00000000", '0'); signal test_data_index : integer := 0; begin -- architecture a1 uut: entity work.an8b10b_decoder @@ -66,8 +66,17 @@ begin -- architecture a1 co_disparity_error <= char.disparity_error; do_8b <= char.d8b; - clk <= not clk after clk_period/2; - reset <= '1' after clk_period*2; + clk_gen: process is + begin -- process clk_gen + wait for clk_period/2; + clk <= not clk; + end process clk_gen; + + reset_gen: process is + begin -- process reset_gen + wait for clk_period*2; + reset <= '1'; + end process reset_gen; test: process is variable test_vec : test_vector; diff --git a/testbench/data_link/char_alignment_tb.vhd b/testbench/data_link/char_alignment_tb.vhd index dd280aa..f8edb6c 100644 --- a/testbench/data_link/char_alignment_tb.vhd +++ b/testbench/data_link/char_alignment_tb.vhd @@ -60,8 +60,17 @@ begin -- architecture a1 ci_synced => ci_synced, co_aligned => co_aligned); - clk <= not clk after clk_period/2; - reset <= '1' after clk_period*2; + clk_gen: process is + begin -- process clk_gen + wait for clk_period/2; + clk <= not clk; + end process clk_gen; + + reset_gen: process is + begin -- process reset_gen + wait for clk_period*2; + reset <= '1'; + end process reset_gen; test: process is variable test_vec : test_vector; diff --git a/testbench/data_link/frame_alignment_tb.vhd b/testbench/data_link/frame_alignment_tb.vhd index 025d284..0a8c9c0 100644 --- a/testbench/data_link/frame_alignment_tb.vhd +++ b/testbench/data_link/frame_alignment_tb.vhd @@ -52,10 +52,10 @@ architecture a1 of frame_alignment_tb is ('0', '1', '1', ('0', '0', '0', "00000000", '0'), ('0', '0', '0', "00000000", 3, 1, '0'), '1', '0'), ('0', '1', '1', ('1', '0', '0', "11111100", '0'), ('0', '0', '0', "11111100", 4, 1, '0'), '1', '0'), ('0', '1', '1', ('1', '0', '0', "01111100", '0'), ('0', '0', '0', "01111100", 0, 2, '0'), '0', '1'), - ('0', '1', '1', ('0', '0', '0', "01111100", '0'), ('0', '0', '0', "01111100", 0, 3, '0'), '0', '1'), - ('0', '1', '1', ('0', '0', '0', "11111111", '0'), ('0', '0', '0', "11111111", 1, 3, '0'), '0', '1'), - ('0', '1', '1', ('0', '0', '0', "11111111", '0'), ('0', '0', '0', "11111111", 2, 3, '0'), '0', '1'), - ('0', '1', '1', ('0', '0', '0', "11111111", '0'), ('0', '0', '0', "11111111", 3, 3, '0'), '0', '1') + ('0', '1', '1', ('0', '0', '0', "01111100", '0'), ('0', '0', '0', "01111100", 0, 3, '0'), '1', '0'), + ('0', '1', '1', ('0', '0', '0', "11111111", '0'), ('0', '0', '0', "11111111", 1, 3, '0'), '1', '0'), + ('0', '1', '1', ('0', '0', '0', "11111111", '0'), ('0', '0', '0', "11111111", 2, 3, '0'), '1', '0'), + ('0', '1', '1', ('0', '0', '0', "11111111", '0'), ('0', '0', '0', "11111111", 3, 3, '0'), '1', '0') ); constant clk_period : time := 1 ns; @@ -92,8 +92,17 @@ begin -- architecture a1 co_error => co_error, do_char => do_char); - clk <= not clk after clk_period/2; - reset <= '1' after clk_period*2; + clk_gen: process is + begin -- process clk_gen + wait for clk_period/2; + clk <= not clk; + end process clk_gen; + + reset_gen: process is + begin -- process reset_gen + wait for clk_period*2; + reset <= '1'; + end process reset_gen; test: process is variable test_vec : test_vector; diff --git a/testbench/data_link/ilas_parser_tb.vhd b/testbench/data_link/ilas_parser_tb.vhd index 75bc99b..4c263b1 100644 --- a/testbench/data_link/ilas_parser_tb.vhd +++ b/testbench/data_link/ilas_parser_tb.vhd @@ -77,154 +77,154 @@ architecture a1 of ilas_parser_tb is constant test_vectors : test_vector_array := ( -- correct sequence, config index 0 - (INIT, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', -1), -- R, 0 mult - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "01111100"), '0', '0', '0', '0', -1), -- A - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', -1), -- R, 1 mult - (ILAS, ('1', '0', '0', "10011100"), '0', '0', '0', '0', -1), -- 28.4 - (ILAS, ('0', '0', '0', "10101010"), '0', '0', '0', '0', -1), -- DID - (ILAS, ('0', '0', '0', "01111110"), '0', '0', '0', '0', -1), -- ADJCNT,BID - (ILAS, ('0', '0', '0', "01101010"), '0', '0', '0', '0', -1), -- X,ADJDIR,PHADJ,LID - (ILAS, ('0', '0', '0', "11011110"), '0', '0', '0', '0', -1), -- SCR,X,L - (ILAS, ('0', '0', '0', "11001100"), '0', '0', '0', '0', -1), -- F - (ILAS, ('0', '0', '0', "01011111"), '0', '0', '0', '0', -1), -- X, K - (ILAS, ('0', '0', '0', "00110011"), '0', '0', '0', '0', -1), -- M - (ILAS, ('0', '0', '0', "10000011"), '0', '0', '0', '0', -1), -- CS,X,N - (ILAS, ('0', '0', '0', "00111101"), '0', '0', '0', '0', -1), -- SUBCLASSV,Nn - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), -- JESDV,S - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "11111111"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00110000"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "01111100"), '0', '0', '0', '0', 0), -- A - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', 0), -- R - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('1', '0', '0', "01111100"), '0', '0', '0', '0', 0), -- A - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', 0), -- R, 2 mult - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', 0), - (ILAS, ('1', '0', '0', "01111100"), '1', '0', '0', '0', 0), -- A - (DATA, ('0', '0', '0', "00000001"), '1', '0', '0', '0', 0), - (DATA, ('0', '0', '0', "00000010"), '1', '0', '0', '0', 0), - (DATA, ('0', '0', '0', "00000011"), '1', '0', '0', '0', 0), + (INIT, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', -1), -- R, 0 mult + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', -1), -- A + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', -1), -- R, 1 mult + (ILS, ('1', '0', '0', "10011100", '0'), '0', '0', '0', '0', -1), -- 28.4 + (ILS, ('0', '0', '0', "10101010", '0'), '0', '0', '0', '0', -1), -- DID + (ILS, ('0', '0', '0', "01111110", '0'), '0', '0', '0', '0', -1), -- ADJCNT,BID + (ILS, ('0', '0', '0', "01101010", '0'), '0', '0', '0', '0', -1), -- X,ADJDIR,PHADJ,LID + (ILS, ('0', '0', '0', "11011110", '0'), '0', '0', '0', '0', -1), -- SCR,X,L + (ILS, ('0', '0', '0', "11001100", '0'), '0', '0', '0', '0', -1), -- F + (ILS, ('0', '0', '0', "01011111", '0'), '0', '0', '0', '0', -1), -- X, K + (ILS, ('0', '0', '0', "00110011", '0'), '0', '0', '0', '0', -1), -- M + (ILS, ('0', '0', '0', "10000011", '0'), '0', '0', '0', '0', -1), -- CS,X,N + (ILS, ('0', '0', '0', "00111101", '0'), '0', '0', '0', '0', -1), -- SUBCLASSV,Nn + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), -- JESDV,S + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "11111111", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00110000", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', 0), -- A + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', 0), -- R + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', 0), -- A + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', 0), -- R, 2 mult + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', 0), + (ILS, ('1', '0', '0', "01111100", '0'), '1', '0', '0', '0', 0), -- A + (DATA, ('0', '0', '0', "00000001", '0'), '1', '0', '0', '0', 0), + (DATA, ('0', '0', '0', "00000010", '0'), '1', '0', '0', '0', 0), + (DATA, ('0', '0', '0', "00000011", '0'), '1', '0', '0', '0', 0), -- incorrect sequence - /R/ at wrong place - (INIT, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', -1), -- R, 0 mult - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "00011100"), '0', '1', '0', '1', -1), -- R, wrong place - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '0', '1', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '0', '1', -1), - (INIT, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), + (INIT, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', -1), -- R, 0 mult + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "00011100", '0'), '0', '1', '0', '1', -1), -- R, wrong place + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '0', '1', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '0', '1', -1), + (INIT, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), -- incorrect sequence - /A/ at wrong place - (INIT, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', -1), -- R, 0 mult - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "01111100"), '0', '1', '0', '1', -1), -- A - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '0', '1', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '0', '1', -1), - (INIT, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), + (INIT, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', -1), -- R, 0 mult + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "01111100", '0'), '0', '1', '0', '1', -1), -- A + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '0', '1', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '0', '1', -1), + (INIT, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), -- incorrect sequence - wrong check sum - (INIT, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (CGS, ('0', '0', '0', "10111100"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', -1), -- R, 0 mult - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('1', '0', '0', "01111100"), '0', '0', '0', '0', -1), -- A - (ILAS, ('1', '0', '0', "00011100"), '0', '0', '0', '0', -1), -- R, 1 mult - (ILAS, ('1', '0', '0', "10011100"), '0', '0', '0', '0', -1), -- 28.4 - (ILAS, ('0', '0', '0', "10101010"), '0', '0', '0', '0', -1), -- DID - (ILAS, ('0', '0', '0', "01111110"), '0', '0', '0', '0', -1), -- ADJCNT,BID - (ILAS, ('0', '0', '0', "01001010"), '0', '0', '0', '0', -1), -- X,ADJDIR,PHADJ,LID - (ILAS, ('0', '0', '0', "11011110"), '0', '0', '0', '0', -1), -- SCR,X,L - (ILAS, ('0', '0', '0', "11001100"), '0', '0', '0', '0', -1), -- F - (ILAS, ('0', '0', '0', "01011111"), '0', '0', '0', '0', -1), -- X, K - (ILAS, ('0', '0', '0', "00110011"), '0', '0', '0', '0', -1), -- M - (ILAS, ('0', '0', '0', "10000011"), '0', '0', '0', '0', -1), -- CS,X,N - (ILAS, ('0', '0', '0', "00111101"), '0', '0', '0', '0', -1), -- SUBCLASSV,Nn - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), -- JESDV,S - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "11111111"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '0', '0', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '1', '0', -1), - (ILAS, ('1', '0', '0', "01111100"), '0', '1', '1', '0', -1), -- A - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '1', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '1', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '1', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '1', '0', -1), - (ILAS, ('0', '0', '0', "00000000"), '0', '1', '1', '0', -1), - (INIT, ('0', '0', '0', "00000000"), '0', '1', '1', '0', -1) + (INIT, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (CGS, ('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', -1), -- R, 0 mult + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('1', '0', '0', "01111100", '0'), '0', '0', '0', '0', -1), -- A + (ILS, ('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', -1), -- R, 1 mult + (ILS, ('1', '0', '0', "10011100", '0'), '0', '0', '0', '0', -1), -- 28.4 + (ILS, ('0', '0', '0', "10101010", '0'), '0', '0', '0', '0', -1), -- DID + (ILS, ('0', '0', '0', "01111110", '0'), '0', '0', '0', '0', -1), -- ADJCNT,BID + (ILS, ('0', '0', '0', "01001010", '0'), '0', '0', '0', '0', -1), -- X,ADJDIR,PHADJ,LID + (ILS, ('0', '0', '0', "11011110", '0'), '0', '0', '0', '0', -1), -- SCR,X,L + (ILS, ('0', '0', '0', "11001100", '0'), '0', '0', '0', '0', -1), -- F + (ILS, ('0', '0', '0', "01011111", '0'), '0', '0', '0', '0', -1), -- X, K + (ILS, ('0', '0', '0', "00110011", '0'), '0', '0', '0', '0', -1), -- M + (ILS, ('0', '0', '0', "10000011", '0'), '0', '0', '0', '0', -1), -- CS,X,N + (ILS, ('0', '0', '0', "00111101", '0'), '0', '0', '0', '0', -1), -- SUBCLASSV,Nn + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), -- JESDV,S + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "11111111", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '1', '0', -1), + (ILS, ('1', '0', '0', "01111100", '0'), '0', '1', '1', '0', -1), -- A + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '1', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '1', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '1', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '1', '0', -1), + (ILS, ('0', '0', '0', "00000000", '0'), '0', '1', '1', '0', -1), + (INIT, ('0', '0', '0', "00000000", '0'), '0', '1', '1', '0', -1) ); constant clk_period : time := 1 ns; @@ -262,8 +262,17 @@ begin -- architecture a1 co_wrong_chksum => co_wrong_chksum, co_unexpected_char => co_unexpected_char); - clk <= not clk after clk_period/2; - reset <= '1' after clk_period*2; + clk_gen: process is + begin -- process clk_gen + wait for clk_period/2; + clk <= not clk; + end process clk_gen; + + reset_gen: process is + begin -- process reset_gen + wait for clk_period*2; + reset <= '1'; + end process reset_gen; test: process is variable test_vec : test_vector; diff --git a/testbench/data_link/lane_alignment_tb.vhd b/testbench/data_link/lane_alignment_tb.vhd index 41e316d..0100243 100644 --- a/testbench/data_link/lane_alignment_tb.vhd +++ b/testbench/data_link/lane_alignment_tb.vhd @@ -22,25 +22,25 @@ architecture a1 of lane_alignment_tb is type test_vector_array is array (natural range<>) of test_vector; constant test_vectors : test_vector_array := ( - --st star kout der mer data expect kout der mer data ready align err - (INIT, '0', ('0', '0', '0', "00000000"), ('1', '0', '0', "10111100"), '0', '0', '0'), - (CGS, '0', ('1', '0', '0', "10111100"), ('1', '0', '0', "10111100"), '0', '0', '0'), - (CGS, '0', ('1', '0', '0', "10111100"), ('1', '0', '0', "10111100"), '0', '0', '0'), - (CGS, '0', ('1', '0', '0', "10111100"), ('1', '0', '0', "10111100"), '0', '0', '0'), - (CGS, '0', ('1', '0', '0', "10111100"), ('1', '0', '0', "10111100"), '0', '0', '0'), - (ILAS, '0', ('1', '0', '0', "01111100"), ('1', '0', '0', "10111100"), '1', '0', '0'), - (ILAS, '0', ('0', '0', '0', "00000000"), ('1', '0', '0', "10111100"), '1', '0', '0'), - (ILAS, '0', ('0', '0', '0', "00000001"), ('1', '0', '0', "10111100"), '1', '0', '0'), - (ILAS, '0', ('0', '0', '0', "00000010"), ('1', '0', '0', "10111100"), '1', '0', '0'), - (DATA, '1', ('0', '0', '0', "00000011"), ('1', '0', '0', "01111100"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00000100"), ('0', '0', '0', "00000000"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00000101"), ('0', '0', '0', "00000001"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00000110"), ('0', '0', '0', "00000010"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00000111"), ('0', '0', '0', "00000011"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001000"), ('0', '0', '0', "00000100"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001001"), ('0', '0', '0', "00000101"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001010"), ('0', '0', '0', "00000110"), '1', '1', '0'), - (DATA, '1', ('0', '0', '0', "00001011"), ('0', '0', '0', "00000111"), '1', '1', '0') + --st star kout der mer data userd expect kout der mer data ready align err + (INIT, '0', ('0', '0', '0', "00000000", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), + (CGS, '0', ('1', '0', '0', "10111100", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), + (CGS, '0', ('1', '0', '0', "10111100", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), + (CGS, '0', ('1', '0', '0', "10111100", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), + (CGS, '0', ('1', '0', '0', "10111100", '0'), ('1', '0', '0', "10111100", '0'), '0', '0', '0'), + (ILS, '0', ('1', '0', '0', "01111100", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), + (ILS, '0', ('0', '0', '0', "00000000", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), + (ILS, '0', ('0', '0', '0', "00000001", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), + (ILS, '0', ('0', '0', '0', "00000010", '0'), ('1', '0', '0', "10111100", '0'), '1', '0', '0'), + (DATA, '1', ('0', '0', '0', "00000011", '0'), ('1', '0', '0', "01111100", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00000100", '0'), ('0', '0', '0', "00000000", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00000101", '0'), ('0', '0', '0', "00000001", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00000110", '0'), ('0', '0', '0', "00000010", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00000111", '0'), ('0', '0', '0', "00000011", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001000", '0'), ('0', '0', '0', "00000100", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001001", '0'), ('0', '0', '0', "00000101", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001010", '0'), ('0', '0', '0', "00000110", '0'), '1', '1', '0'), + (DATA, '1', ('0', '0', '0', "00001011", '0'), ('0', '0', '0', "00000111", '0'), '1', '1', '0') ); constant clk_period : time := 1 ns; @@ -76,10 +76,20 @@ begin -- architecture a1 co_aligned => co_aligned, co_error => co_error, co_ready => co_ready, - do_char => do_char); - - clk <= not clk after clk_period/2; - reset <= '1' after clk_period*2; + do_char => do_char, + ci_realign => '0'); + + clk_gen: process is + begin -- process clk_gen + wait for clk_period/2; + clk <= not clk; + end process clk_gen; + + reset_gen: process is + begin -- process reset_gen + wait for clk_period*2; + reset <= '1'; + end process reset_gen; test: process is variable test_vec : test_vector; diff --git a/testbench/data_link/link_controller_tb.vhd b/testbench/data_link/link_controller_tb.vhd index ea4c0a9..0186676 100644 --- a/testbench/data_link/link_controller_tb.vhd +++ b/testbench/data_link/link_controller_tb.vhd @@ -82,109 +82,109 @@ architecture a1 of link_controller_tb is type test_vector_array is array (natural range<>) of test_vector; constant test_vectors : test_vector_array := ( - --kout der noter char resync ler lal lre fer fal expsyn expstexpuner exper expconf - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '1', CGS, '0', '0', -1), - (('1', '0', '0', "00011100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --R - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('1', '0', '0', "01111100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --A - (('1', '0', '0', "00011100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --R - (('0', '0', '0', "10011100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "10101010"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "01111110"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "01101010"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "11011110"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "11001100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "01011111"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00110011"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "10000011"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00111101"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "11111111"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('0', '0', '0', "00110000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), - (('1', '0', '0', "01111100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --A - (('1', '0', '0', "00011100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --R - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('1', '0', '0', "01111100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --A - (('1', '0', '0', "00011100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --R - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), - (('1', '0', '0', "01111100"), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', 0), --A - (('0', '0', '0', "01010101"), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), - (('0', '0', '0', "01010101"), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), - (('0', '0', '0', "01010101"), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), - (('0', '0', '0', "01010101"), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), - (('0', '0', '0', "01010101"), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '0', 0), - (('0', '0', '1', "01010101"), '0', '0', '0', '0', '0', '0', '1', DATA, '0', '1', 0), - (('0', '0', '0', "01010101"), '0', '1', '0', '0', '0', '0', '1', DATA, '0', '1', 0), - (('0', '0', '0', "01010101"), '0', '1', '0', '0', '1', '0', '1', DATA, '0', '1', 0), - (('0', '0', '0', "01010101"), '0', '0', '0', '0', '1', '0', '1', DATA, '0', '1', 0), - (('0', '0', '0', "01010101"), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "01010101"), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "01010101"), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '1', CGS, '0', '0', -1), - (('1', '0', '0', "10111100"), '0', '0', '0', '0', '0', '0', '1', CGS, '0', '0', -1), - (('0', '0', '0', "00000000"), '1', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), - (('0', '0', '0', "00000000"), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1) + --kout der noter char userd resync ler lal lre fer fal expsyn expstexpuner exper expconf + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1), + (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), + (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), + (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), + (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '0', CGS, '0', '0', -1), + (('1', '0', '0', "10111100", '0'), '0', '0', '0', '0', '0', '0', '1', CGS, '0', '0', -1), + (('1', '0', '0', "00011100", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), --R + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '1', ILS, '0', '0', -1), + (('0', '0', '0', "00000000", '0'), '0', '0', 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clk after clk_period/2; - reset <= '1' after clk_period*2; + clk_gen: process is + begin -- process clk_gen + wait for clk_period/2; + clk <= not clk; + end process clk_gen; + + reset_gen: process is + begin -- process reset_gen + wait for clk_period*2; + reset <= '1'; + end process reset_gen; test: process is variable test_vec : test_vector; -- 2.48.1