2 files changed, 20 insertions(+), 50 deletions(-)

M src/descrambler.vhd
M src/jesd204b_rx.vhd

@@ 3,60 3,27 @@ use ieee.std_logic_1164.all;
 use work.data_link_pkg.all;
 
 entity descrambler is
+  generic (
+    F : integer);
   port (
-    ci_char_clk : in  std_logic;
+    ci_frame_clk : in  std_logic;
     ci_reset    : in  std_logic;
-    di_char     : in  frame_character;
-    do_char     : out frame_character);
+    di_data     : in  std_logic_vector(8*F - 1 downto 0);
+    do_data     : out std_logic_vector(8*F - 1 downto 0));
 
 end entity descrambler;
 
--- see 8-bit parallel implementation of self-synchronous descrambler based on
 -- 1+x^14 + x^15
 -- in JESD204 specification Annex D
 architecture a1 of descrambler is
-  signal S : std_logic_vector(23 downto 1);
-  signal D : std_logic_vector(23 downto 16);
-  signal reg_char : frame_character;
-
-  signal next_S : std_logic_vector(15 downto 1);
-
-  function reverseOrder (
-    data : std_logic_vector(7 downto 0))
-    return std_logic_vector
-  is
-    variable result : std_logic_vector(7 downto 0);
-  begin
-    for i in 0 to 7 loop
-      result(7 - i) := data(i);
-    end loop;  -- i
-    return result;
-  end function reverseOrder;
 begin  -- architecture a1
   set_next: process (ci_char_clk, ci_reset) is
   begin  -- process set_next
     if ci_reset = '0' then              -- asynchronous reset (active low)
-      reg_char <= ('0', '0', '0', "00000000", 0, 0, '0');
-      S(15 downto 1) <= (others => '0');
+      do_data <= (others => '0');
     elsif ci_char_clk'event and ci_char_clk = '1' then  -- rising clock edge
-      S(15 downto 1) <= next_S(15 downto 1);
+      do_data <= di_data; -- TODO: implement the descrambler...
     end if;
   end process set_next;
 
-  do_char.d8b(7 downto 0) <= reverseOrder(D(23 downto 16)) when reg_char.user_data = '1' else reg_char.d8b(7 downto 0);
-  do_char.kout <= reg_char.kout;
-  do_char.user_data <= reg_char.user_data;
-  do_char.disparity_error <= reg_char.disparity_error;
-  do_char.missing_error <= reg_char.missing_error;
-  do_char.octet_index <= reg_char.octet_index;
-  do_char.frame_index <= reg_char.frame_index;
-
-  S(23 downto 16) <= reverseOrder(di_char.d8b(7 downto 0));
-  next_S(15 downto 8) <= S(23 downto 16);
-  next_S(7 downto 1) <= S(15 downto 9);
-
-  descrambled_generator: for i in 16 to 23 generate
-    D(i) <= (S(i-15) xor S(i-14)) xor S(i);
-  end generate descrambled_generator;
-
 end architecture a1;

@@ 62,7 62,7 @@ architecture a1 of jesd204b_rx is
   signal data_link_start : std_logic := '0';
 
   -- == DESCRAMBLER ==
-  -- signal scrambler_chars_array : frame_character_array(0 to L-1);
+  signal descrambler_aligned_chars_array : lane_character_array(0 to L-1)(F*8-1 downto 0);
 
   -- == TRANSPORT ==
   signal transport_chars_array : lane_character_array(0 to L-1)(F*8-1 downto 0);


@@ 96,9 96,10 @@ begin  -- architecture a1
   data_link_start <= '1' when data_link_ready_vector = all_ones else '0';
 
   -- characters either from scrambler if scrambling enabled or directly from data_link
-  -- transport_chars_array <= scrambler_chars_array when SCRAMBLING = '1' else data_link_chars_array;
-  transport_chars_array <= data_link_aligned_chars_array;
-  transport_frame_state_array <= data_link_frame_state_array;
+  transport_chars_array <= scrambler_aligned_chars_array when SCRAMBLING = '1' else data_link_aligned_chars_array;
+  transport_frame_state_array <= data_link_frame_state_array; -- TODO: buffer
+                                                              -- frame_state if
+                                                              -- scrambling
 
   -- error '1' if configs do not match
   co_error <= not ConfigsMatch(lane_configuration_array);


@@ 127,12 128,14 @@ begin  -- architecture a1
         co_frame_state   => data_link_frame_state_array(i));
 
     scrambler_gen: if SCRAMBLING = '1' generate
-      -- scrambler: entity work.descrambler
-      --   port map (
-      --     ci_char_clk => ci_char_clk,
-      --     ci_reset    => ci_reset,
-      --     di_char     => data_link_chars_array(i),
-      --     do_char     => scrambler_chars_array(i));
+      scrambler: entity work.descrambler
+        generic map (
+          F => F)
+        port map (
+          ci_frame_clk => ci_frame_clk,
+          ci_reset    => ci_reset,
+          di_char     => data_link_aligned_chars_array(i),
+          do_char     => descrambler_aligned_chars_array(i));
     end generate scrambler_gen;
   end generate data_links;