2 files changed, 7 insertions(+), 2 deletions(-)

M src/data_link/data_link_layer.vhd
M src/jesd204b_rx.vhd

@@ 44,6 44,7 @@ entity data_link_layer is
     -- synchronization
     co_lane_ready : out std_logic;  -- Received /A/, waiting for lane sync
     ci_lane_start : in  std_logic;  -- Start sending data from lane buffer
+    ci_request_sync : in std_logic; -- Request resynchronization
 
     -- input, output
     co_synced        : out std_logic;  -- Whether the lane is synced


@@ 57,6 58,8 @@ architecture a1 of data_link_layer is
 
   signal decoder_do_char : character_vector;
 
+  signal error_handler_co_request_sync : std_logic;
+
   signal lane_alignment_ci_realign            : std_logic := '0';
   signal lane_alignment_co_aligned            : std_logic;
   signal lane_alignment_co_error              : std_logic;


@@ 95,7 98,6 @@ begin  -- architecture a1
   -- error handling
   error_handling : entity work.error_handler
     generic map (
-      F => F)
       F => F,
       CONFIG => ERROR_CONFIG)
     port map (


@@ 109,9 111,10 @@ begin  -- architecture a1
       ci_frame_alignment_correct_count => frame_alignment_co_correct_sync_chars,
       co_frame_alignment_realign       => frame_alignment_ci_realign,
       co_lane_alignment_realign        => lane_alignment_ci_realign,
-      co_request_sync                  => link_controller_ci_resync);
+      co_request_sync                  => error_handler_co_request_sync);
 
   -- link controller
+  link_controller_ci_resync <= error_handler_co_request_sync or ci_request_sync;
   link_controller : entity work.link_controller
     generic map (
       F => F,

@@ 38,6 38,7 @@ entity jesd204b_rx is
     ci_char_clk  : in std_logic;        -- Character clock
     ci_frame_clk : in std_logic;        -- Frame clock
     ci_reset     : in std_logic;        -- Reset (asynchronous, active low)
+    ci_request_sync : in std_logic;     -- Request synchronization
 
     co_lane_config : out link_config;   -- The configuration of the link
     co_nsynced     : out std_logic;     -- Whether receiver is synced (active low)


@@ 122,6 123,7 @@ begin  -- architecture a1
         do_lane_config   => lane_configuration_array(i),
         co_lane_ready    => data_link_ready_vector(i),
         ci_lane_start    => data_link_start,
+        ci_request_sync  => ci_request_sync,
         co_synced        => data_link_synced_vector(i),
         di_10b           => di_transceiver_data(i),
         do_aligned_chars => data_link_aligned_chars_array(i),