2 files changed, 4 insertions(+), 35 deletions(-)

M src/data_link/char_alignment.vhd
D testbench/char_alignment_tb.vhd

@@ 15,7 15,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity char_alignment is
-  
+
   generic (
     sync_char : std_logic_vector(9 downto 0) := "0011111010"  -- The character used for synchronization (positive RD)
     );


@@ 32,7 32,7 @@ end entity char_alignment;
 architecture a1 of char_alignment is
   signal next_cache_10b : std_logic_vector(19 downto 0) := (others => '0');  -- The next value of cache_10b
   signal next_do_10b : std_logic_vector(9 downto 0) := (others => '0');  -- The next value of do_10b
-  signal next_co_aligned : std_logic := '0';  
+  signal next_co_aligned : std_logic := '0';
 
   signal reg_found_sync_char : std_logic := '0';  -- Whether sync char was found
   signal reg_cache_10b : std_logic_vector(19 downto 0) := (others => '0');  -- The cache of 10b characters.


@@ 79,9 79,9 @@ begin  -- architecture a1
       if ci_synced = '0' then
         -- Try to find /K/ (sync_char) in either RD (either sync_char or not sync_char).
         for i in 0 to 9 loop
-          if reg_cache_10b((9-i)+9 downto (9-i)) = sync_char or reg_cache_10b((9-i)+9 downto (9-i)) = not sync_char then
+          if reg_cache_10b(i+9 downto i) = sync_char or reg_cache_10b(i+9 downto i) = not sync_char then
             reg_found_sync_char <= '1';
-            reg_alignment_index <= 9 - i;
+            reg_alignment_index <= i;
           end if;
         end loop;  -- i
       end if;

@@ 1,31 0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity char_alignment_tb is
-end entity char_alignment_tb;
-
-architecture a1 of char_alignment_tb is
-  constant clk_period : time := 1 ns;    -- The clock period
-  constant buffer_positions : integer := 2;
-
-  signal clk : std_logic := '0';        -- The clock
-  signal reset : std_logic := '0';      -- The reset
-
-  signal synced : std_logic := '0';     -- Whether synced
-  signal data_10b : std_logic_vector(9 downto 0) := (others => '0');  -- The 10b data input
-
-  signal buffer_position : integer := 0;
-  signal data_10b_buffer : std_logic_vector(10*2-1 downto 0) := "00111100110011110011";  -- The 10b data input
-begin  -- architecture a1
-  uut: entity work.char_alignment
-    port map (
-      ci_char_clk => clk,
-      ci_reset    => reset,
-      di_10b      => data_10b,
-      ci_synced   => synced);
-
-  data_10b <= data_10b_buffer(buffer_position*10+9 downto buffer_position*10);
-  buffer_position <= (buffer_position + 1) mod buffer_positions after clk_period;
-  clk <= not clk after clk_period/2;
-  reset <= '1' after clk_period*2;
-end architecture a1;