From 87f51b4abb1911b51600255fcf9d1878eefbd28e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Mon, 19 Dec 2022 19:00:30 +0100 Subject: [PATCH] chore: add documentation to the code --- src/data_link/an8b10b_decoder.vhd | 19 ++++++++--- src/data_link/char_alignment.vhd | 4 +-- src/data_link/data_link_layer.vhd | 53 ++++++++++++++++++---------- src/data_link/data_link_pkg.vhd | 19 +++++++---- src/data_link/error_handler.vhd | 45 +++++++++++++++++------- src/data_link/frame_alignment.vhd | 42 ++++++++++++++++++----- src/data_link/ilas_parser.vhd | 48 ++++++++++++++++++-------- src/data_link/lane_alignment.vhd | 50 +++++++++++++++++++-------- src/data_link/link_controller.vhd | 55 +++++++++++++++++++++--------- src/jesd204b_pkg.vhd | 1 + src/jesd204b_rx.vhd | 39 ++++++++++++++------- src/transport/octets_to_sample.vhd | 29 ++++++++++++---- src/transport/transport_layer.vhd | 25 ++++++++++---- src/transport/transport_pkg.vhd | 5 +++ 14 files changed, 310 insertions(+), 124 deletions(-) diff --git a/src/data_link/an8b10b_decoder.vhd b/src/data_link/an8b10b_decoder.vhd index 546d68f..4bbfa30 100644 --- a/src/data_link/an8b10b_decoder.vhd +++ b/src/data_link/an8b10b_decoder.vhd @@ -1,3 +1,14 @@ +------------------------------------------------------------------------------- +-- Title : 8b10b decoder +------------------------------------------------------------------------------- +-- File : an8b10b_decoder.vhd +------------------------------------------------------------------------------- +-- Description: Decodes 8b10b encoding, outputs 8bit. Expects aligned characters +-- at input. Outputs do_char with disparity error and missing (not in table) errors. +-- For first character it's possible to get a disparity error. +------------------------------------------------------------------------------- + + library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; @@ -7,11 +18,11 @@ use work.data_link_pkg.all; entity an8b10b_decoder is port ( ci_char_clk : in std_logic; -- The character clock - ci_reset : in std_logic; -- The reset + ci_reset : in std_logic; -- The reset (asynchronous active low) di_10b : in std_logic_vector(9 downto 0); -- The 8b10b encoded input data - do_char : out character_vector; -- The output character vector - co_error : out std_logic); -- Whether there is an error - -- (disparity or invalid character) + do_char : out character_vector; -- The output decoded 8b data + co_error : out std_logic); -- Whether there is an error (disparity + -- or missing) end entity an8b10b_decoder; architecture a1 of an8b10b_decoder is diff --git a/src/data_link/char_alignment.vhd b/src/data_link/char_alignment.vhd index 66ec19d..ff51896 100644 --- a/src/data_link/char_alignment.vhd +++ b/src/data_link/char_alignment.vhd @@ -4,8 +4,8 @@ ------------------------------------------------------------------------------- -- File : char_alignment.vhd -- Description: Tries to align the beginning of the character from 8b/10b encoding. --- Accepting 10 bits, outputting 8 bits. Will try to sync to /K/ character when --- synced is false. +-- Accepting 10 bits, outputting 10 bits. Will try to sync to /K/ character when +-- ci_synced is false. ------------------------------------------------------------------------------- -- input d_in[9:0], ci_synced diff --git a/src/data_link/data_link_layer.vhd b/src/data_link/data_link_layer.vhd index 2037a6d..e3c09e7 100644 --- a/src/data_link/data_link_layer.vhd +++ b/src/data_link/data_link_layer.vhd @@ -1,35 +1,52 @@ +------------------------------------------------------------------------------- +-- Title : data link +------------------------------------------------------------------------------- +-- File : data_link_layer.vhd +------------------------------------------------------------------------------- +-- Description: A wrapper entity for data link components. +-- Receives 10b characters, outputs aligned frame 8b characters +-- Connects: +-- +-- ############################## DATA LINK ################################### +-- char_alignment => 8b10bdecoder => lane_alignment => frame_alignment +-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +-- error_handler +-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +-- link_controller +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; entity data_link_layer is generic ( - K_character : std_logic_vector(7 downto 0) := "10111100"; - R_character : std_logic_vector(7 downto 0) := "00011100"; - A_character : std_logic_vector(7 downto 0) := "01111100"; - Q_character : std_logic_vector(7 downto 0) := "10011100"; - ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5); - SCRAMBLING : std_logic := '0'; - F : integer := 2; - K : integer := 1); + K_character : std_logic_vector(7 downto 0) := "10111100"; -- K sync character + R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS + -- multiframe start + A_character : std_logic_vector(7 downto 0) := "01111100"; -- multiframe end + Q_character : std_logic_vector(7 downto 0) := "10011100"; -- 2nd ILAS frame + -- 2nd character + ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5); -- Configuration + -- for the error + SCRAMBLING : std_logic := '0'; -- Whether scrambling is enabled + F : integer := 2; -- Number of octets in a frame + K : integer := 1); -- Number of frames in a mutliframe port ( - ci_char_clk : in std_logic; - ci_reset : in std_logic; + ci_char_clk : in std_logic; -- Character clock + ci_reset : in std_logic; -- Reset (asynchronous, active low) -- link configuration - do_lane_config : out link_config; + do_lane_config : out link_config; -- Configuration of the link -- synchronization co_lane_ready : out std_logic; -- Received /A/, waiting for lane sync ci_lane_start : in std_logic; -- Start sending data from lane buffer - -- errors - ci_error_config : in error_handling_config; - -- input, output - co_synced : out std_logic; - di_10b : in std_logic_vector(9 downto 0); - do_char : out frame_character); + co_synced : out std_logic; -- Whether the lane is synced + di_10b : in std_logic_vector(9 downto 0); -- The 10b input character + do_char : out frame_character); -- The aligned frame output character end entity data_link_layer; architecture a1 of data_link_layer is @@ -77,7 +94,7 @@ begin -- architecture a1 ci_state => link_controller_co_state, ci_F => F, di_char => decoder_do_char, - ci_config => ci_error_config, + ci_config => ERROR_CONFIG, ci_lane_alignment_error => lane_alignment_co_error, ci_frame_alignment_error => frame_alignment_co_error, ci_lane_alignment_correct_count => lane_alignment_co_correct_sync_chars, diff --git a/src/data_link/data_link_pkg.vhd b/src/data_link/data_link_pkg.vhd index d3a4321..9301d9f 100644 --- a/src/data_link/data_link_pkg.vhd +++ b/src/data_link/data_link_pkg.vhd @@ -8,7 +8,8 @@ package data_link_pkg is disparity_error : std_logic; -- Whether there was a disparity error (if this is true, the character will still be correct) missing_error : std_logic; -- Whether the character was not found in the table d8b : std_logic_vector(7 downto 0); -- The decoded data - user_data : std_logic; + user_data : std_logic; -- Whether the data is user data (in + -- DATA state, false otherwise) end record character_vector; type frame_character is record @@ -16,15 +17,19 @@ package data_link_pkg is disparity_error : std_logic; -- Whether there was a disparity error (if this is true, the character will still be correct) missing_error : std_logic; -- Whether the character was not found in the table d8b : std_logic_vector(7 downto 0); -- The decoded data - octet_index : integer range 0 to 256; - frame_index : integer range 0 to 32; - user_data : std_logic; + octet_index : integer range 0 to 256; -- The position of the octet in a + -- frame + frame_index : integer range 0 to 32; -- The position of the frame in multiframe + user_data : std_logic; -- Whether the data is user data (in + -- DATA state, false otherwise) end record frame_character; type link_state is ( - INIT, - CGS, - ILS, + INIT, -- Initial state, waiting for /K/ characters + CGS, -- Code group synchronization, after + -- receiving /K/ character + ILS, -- Initial lane synchronization + -- (containing link configuration) DATA); -- States of the link type link_config is record diff --git a/src/data_link/error_handler.vhd b/src/data_link/error_handler.vhd index 8c0407f..0a4ac37 100644 --- a/src/data_link/error_handler.vhd +++ b/src/data_link/error_handler.vhd @@ -1,26 +1,47 @@ +------------------------------------------------------------------------------- +-- Title : error handler +------------------------------------------------------------------------------- +-- File : error_handler.vhd +------------------------------------------------------------------------------- +-- Description: Processes errors given the allowed number of errors +-- configuration. Outputs request_sync if more than allowed number +-- of errors was reached. +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; entity error_handler is port ( - ci_char_clk : in std_logic; - ci_reset : in std_logic; - ci_state : in link_state; + ci_char_clk : in std_logic; -- Character clock + ci_reset : in std_logic; -- Reset (asynchronous, + -- active low) + ci_state : in link_state; -- State of the lane. ci_F : in integer range 0 to 256; - di_char : in character_vector; + di_char : in character_vector; -- Character from + -- 8b10b decoder - ci_config : in error_handling_config; - ci_lane_alignment_error : in std_logic; - ci_lane_alignment_correct_count : in integer; - ci_frame_alignment_error : in std_logic; - ci_frame_alignment_correct_count : in integer; + ci_config : in error_handling_config; -- + --Configuration + --of error handling + ci_lane_alignment_error : in std_logic; -- Signals an error with + -- lane alignment + ci_lane_alignment_correct_count : in integer; -- Signals number of + -- alignment characters on + -- the same position + ci_frame_alignment_error : in std_logic; -- Signals an error with + -- frame alignment + ci_frame_alignment_correct_count : in integer; -- Signals number of + -- alignemnt characters on + -- the same position - co_frame_alignment_realign : out std_logic; - co_lane_alignment_realign : out std_logic; - co_request_sync : out std_logic); + co_frame_alignment_realign : out std_logic; -- Output to realign + -- frame + co_lane_alignment_realign : out std_logic; -- Output to realign lane + co_request_sync : out std_logic); -- Request a synchronization end entity error_handler; architecture a1 of error_handler is diff --git a/src/data_link/frame_alignment.vhd b/src/data_link/frame_alignment.vhd index 540402c..a93738f 100644 --- a/src/data_link/frame_alignment.vhd +++ b/src/data_link/frame_alignment.vhd @@ -1,27 +1,51 @@ +------------------------------------------------------------------------------- +-- Title : frame alignment +------------------------------------------------------------------------------- +-- File : frame_alignment.vhd +------------------------------------------------------------------------------- +-- Description: Retrieves alignment of octet in a frame. +-- Aligns using /A/ and /F/ characters. If these characters are on wrong spot, +-- returns an error. May realign if requested. + +-- IF lane alignment is in use (more lanes are there), do not realign using +-- frame alignment. Realign using lane alignment. ci_realign of frame alignment +-- should remain low at all times. +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; entity frame_alignment is generic ( - sync_char : std_logic_vector(7 downto 0) := "10111100"; - A_char : std_logic_vector(7 downto 0) := "01111100"; - F_char : std_logic_vector(7 downto 0) := "11111100"; + sync_char : std_logic_vector(7 downto 0) := "10111100"; -- K + -- character + -- for syncing + A_char : std_logic_vector(7 downto 0) := "01111100"; -- Last + -- character + -- in multiframe + F_char : std_logic_vector(7 downto 0) := "11111100"; -- Last + -- character + -- in frame F_replace_data : std_logic_vector(7 downto 0) := "11111100"; -- The character to replace with upon receiving /F/ with scrambled data A_replace_data : std_logic_vector(7 downto 0) := "01111100"); -- The character to replace with upon receiving /A/ with scrambled data port ( - ci_char_clk : in std_logic; - ci_reset : in std_logic; + ci_char_clk : in std_logic; -- Character clock + ci_reset : in std_logic; -- Reset (asynchronous, active low) ci_F : in integer range 0 to 256; -- The number of octets in a frame ci_K : in integer range 0 to 32; -- The number of frames in a multiframe ci_request_sync : in std_logic; -- Whether sync is requested ci_scrambled : in std_logic; -- Whether the data is scrambled - ci_realign : in std_logic; + ci_realign : in std_logic; -- Whether to realign to last + -- alignment character di_char : in character_vector; -- The received character - co_aligned : out std_logic; - co_error : out std_logic; - co_correct_sync_chars : out integer; + co_aligned : out std_logic; -- Whether the alignment is right + co_error : out std_logic; -- Whether there was an error with + -- the alignment + co_correct_sync_chars : out integer; -- Number of alignment characters on + -- same position in a row do_char : out frame_character); -- The output character + -- (going to transport layer) end entity frame_alignment; architecture a1 of frame_alignment is diff --git a/src/data_link/ilas_parser.vhd b/src/data_link/ilas_parser.vhd index 1f570d3..7be8732 100644 --- a/src/data_link/ilas_parser.vhd +++ b/src/data_link/ilas_parser.vhd @@ -1,3 +1,12 @@ +------------------------------------------------------------------------------- +-- Title : ilas parser +------------------------------------------------------------------------------- +-- File : ilas_parser.vhd +------------------------------------------------------------------------------- +-- Description: Parses ilas, outputs it's config and checks +-- that everything is correct. +------------------------------------------------------------------------------- + library ieee; use work.data_link_pkg.all; use ieee.std_logic_1164.all; @@ -5,24 +14,33 @@ use ieee.numeric_std.all; entity ilas_parser is generic ( - K_character : std_logic_vector(7 downto 0) := "10111100"; - R_character : std_logic_vector(7 downto 0) := "00011100"; - A_character : std_logic_vector(7 downto 0) := "01111100"; - Q_character : std_logic_vector(7 downto 0) := "10011100"; -- 9C + K_character : std_logic_vector(7 downto 0) := "10111100"; -- Character + -- for syncing + R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS + -- multiframe + -- start character + A_character : std_logic_vector(7 downto 0) := "01111100"; -- ILAS + -- multiframe + -- end character + Q_character : std_logic_vector(7 downto 0) := "10011100"; -- ILAS 2nd + -- multiframe + -- 2nd character multiframes_count : integer := 4); port ( - ci_char_clk : in std_logic; - ci_reset : in std_logic; - ci_F : in integer range 0 to 256; - ci_K : in integer range 0 to 32; - ci_state : in link_state; - di_char : in character_vector; - do_config : out link_config; - co_finished : out std_logic; - co_error : out std_logic; - co_wrong_chksum : out std_logic; - co_unexpected_char : out std_logic); + ci_char_clk : in std_logic; -- Character clock + ci_reset : in std_logic; -- Reset (asynchonous, active low) + ci_F : in integer range 0 to 256; -- Number of octets in a + -- frame + ci_K : in integer range 0 to 32; -- Number of frames in a multiframe + ci_state : in link_state; -- State of the lane + di_char : in character_vector; -- Character from 8b10b decoder + do_config : out link_config; -- Config found in ILAS + co_finished : out std_logic; -- The ILAS was received correctly + co_error : out std_logic; -- The ILAS was not received correctly + co_wrong_chksum : out std_logic; -- There was a wrong checksum in the ILAS + co_unexpected_char : out std_logic); -- There was a character at + -- unexpected location in the ILAS end entity ilas_parser; diff --git a/src/data_link/lane_alignment.vhd b/src/data_link/lane_alignment.vhd index 87a8a90..1f73f25 100644 --- a/src/data_link/lane_alignment.vhd +++ b/src/data_link/lane_alignment.vhd @@ -1,27 +1,47 @@ +------------------------------------------------------------------------------- +-- Title : Lane alignment +------------------------------------------------------------------------------- +-- File : lane_alignment.vhd +------------------------------------------------------------------------------- +-- Description: Ensures all lanes are aligned to the same character. +-- Buffers after receiving first /A/ character until ci_start is set. +-- Then starts sending the data from the buffer. +-- That ensures all the lanes start at the same position. +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; entity lane_alignment is generic ( - buffer_size : integer := 256; - alignment_character : std_logic_vector(7 downto 0) := "01111100"; + buffer_size : integer := 256; -- How many octets to keep + alignment_character : std_logic_vector(7 downto 0) := "01111100"; -- The K + -- + --alignment character dummy_character : character_vector := ('1', '0', '0', "10111100", '0')); +-- Character to send before the buffer is ready and started port ( - ci_char_clk : in std_logic; - ci_reset : in std_logic; - ci_start : in std_logic; - ci_state : in link_state; - ci_realign : in std_logic; - ci_F : in integer range 0 to 256; - ci_K : in integer range 0 to 32; - di_char : in character_vector; - co_ready : out std_logic; - co_aligned : out std_logic; - co_correct_sync_chars : out integer; - co_error : out std_logic; - do_char : out character_vector); + ci_char_clk : in std_logic; -- Character clock + ci_reset : in std_logic; -- Reset (asynchronous, active low) + ci_start : in std_logic; -- Start sending the data from the + -- buffer. + ci_state : in link_state; -- State of the lane + ci_realign : in std_logic; -- Whether to realign to the last + -- found alignment character + ci_F : in integer range 0 to 256; -- Number of octets in + -- a frame + ci_K : in integer range 0 to 32; -- Number of frames in + -- a multiframe + di_char : in character_vector; -- Character from 8b10b decoder + co_ready : out std_logic; -- Whether /A/ was received and + -- waiting for start + co_aligned : out std_logic; -- Whether the alignment is still correct + co_correct_sync_chars : out integer; -- How many alignment characters on + -- correct place were found in a row + co_error : out std_logic; -- Whether there is an error + do_char : out character_vector); -- The aligned output character end entity lane_alignment; diff --git a/src/data_link/link_controller.vhd b/src/data_link/link_controller.vhd index 627320c..c54e44d 100644 --- a/src/data_link/link_controller.vhd +++ b/src/data_link/link_controller.vhd @@ -1,3 +1,12 @@ +------------------------------------------------------------------------------- +-- Title : controller of data link layer +------------------------------------------------------------------------------- +-- File : link_controller.vhd +------------------------------------------------------------------------------- +-- Description: Controller for link layer, handling CGS and ILAS. +-- +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; @@ -11,30 +20,42 @@ use work.data_link_pkg.all; entity link_controller is generic ( - K_character : std_logic_vector(7 downto 0) := "10111100"); + K_character : std_logic_vector(7 downto 0) := "10111100"); -- Sync character port ( - ci_char_clk : in std_logic; - ci_reset : in std_logic; - di_char : in character_vector; + ci_char_clk : in std_logic; -- Character clock + ci_reset : in std_logic; -- Reset (asynchronous, active low) + di_char : in character_vector; -- Output character from 8b10b decoder - do_config : out link_config; + do_config : out link_config; -- Config found in ILAS - ci_F : in integer range 0 to 256; - ci_K : in integer range 0 to 32; + ci_F : in integer range 0 to 256; -- Number of octets in a frame + ci_K : in integer range 0 to 32; -- Number of frames in a multiframe - ci_lane_alignment_error : in std_logic; - ci_lane_alignment_aligned : in std_logic; - ci_lane_alignment_ready : in std_logic; + ci_lane_alignment_error : in std_logic; -- Signals a problem with lane + -- alignment in this data link + -- (see lane alighnment component) + ci_lane_alignment_aligned : in std_logic; -- Signals that lane is + -- correctly aligned (see + -- lane_alignment component) + ci_lane_alignment_ready : in std_logic; -- Signals that the lane received + -- /A/ and is waiting to start + -- sending data (see + -- lane_alignment component) - ci_frame_alignment_error : in std_logic; - ci_frame_alignment_aligned : in std_logic; + ci_frame_alignment_error : in std_logic; -- Signals that the frame was misaligned. + ci_frame_alignment_aligned : in std_logic; -- Signals that the frame end + -- was found and did not change. - ci_resync : in std_logic; + ci_resync : in std_logic; -- Whether to start syncing again. - co_synced : out std_logic; - co_state : out link_state; - co_uncorrectable_error : out std_logic; - co_error : out std_logic); + co_synced : out std_logic; -- Whether the lane is synced (received + -- 4 /K/ characters and proceeds correctly) + co_state : out link_state; -- The state of the lane. + co_uncorrectable_error : out std_logic; -- Detected an uncorrectable + -- error, has to resync (ilas + -- parsing error) + co_error : out std_logic); -- Detected any error, processing may + -- differ end entity link_controller; architecture a1 of link_controller is diff --git a/src/jesd204b_pkg.vhd b/src/jesd204b_pkg.vhd index a213982..5ff7773 100644 --- a/src/jesd204b_pkg.vhd +++ b/src/jesd204b_pkg.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; +-- Package for jesd204b types package jesd204b_pkg is -- array input data from lanes diff --git a/src/jesd204b_rx.vhd b/src/jesd204b_rx.vhd index 933a7f5..c7ec039 100644 --- a/src/jesd204b_rx.vhd +++ b/src/jesd204b_rx.vhd @@ -1,3 +1,12 @@ +------------------------------------------------------------------------------- +-- Title : JESD204B receiver +------------------------------------------------------------------------------- +-- File : jesd204b_rx.vhd +------------------------------------------------------------------------------- +-- Description: A top level entity for a JESD204B receiver. +-- Holds data_link and transport_layers. +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.transport_pkg.all; @@ -6,11 +15,15 @@ use work.jesd204b_pkg.all; entity jesd204b_rx is generic ( - K_character : std_logic_vector(7 downto 0) := "10111100"; - R_character : std_logic_vector(7 downto 0) := "00011100"; - A_character : std_logic_vector(7 downto 0) := "01111100"; - Q_character : std_logic_vector(7 downto 0) := "10011100"; - K : integer := 1; + K_character : std_logic_vector(7 downto 0) := "10111100"; -- Sync character + R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS first + -- frame character + A_character : std_logic_vector(7 downto 0) := "01111100"; -- Multiframe + -- alignment character + Q_character : std_logic_vector(7 downto 0) := "10011100"; -- ILAS 2nd + -- frame 2nd character + K : integer := 1; -- Number of frames in a + -- multiframe CS : integer := 1; -- Number of control bits per sample M : integer := 1; -- Number of converters S : integer := 1; -- Number of samples @@ -22,17 +35,19 @@ entity jesd204b_rx is ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5); SCRAMBLING : std_logic := '0'); port ( - ci_char_clk : in std_logic; - ci_frame_clk : in std_logic; - ci_reset : in std_logic; + ci_char_clk : in std_logic; -- Character clock + ci_frame_clk : in std_logic; -- Frame clock + ci_reset : in std_logic; -- Reset (asynchronous, active low) - co_lane_config : out link_config; - co_nsynced : out std_logic; + co_lane_config : out link_config; -- The configuration of the link + co_nsynced : out std_logic; -- Whether receiver is synced (active low) co_error : out std_logic; - di_transceiver_data : in lane_input_array(L-1 downto 0); + di_transceiver_data : in lane_input_array(L-1 downto 0); -- Data from transceivers do_samples : out samples_array(M - 1 downto 0, S - 1 downto 0); - co_correct_data : out std_logic); +-- Output samples + co_correct_data : out std_logic); -- Whether samples are correct user + -- data end entity jesd204b_rx; architecture a1 of jesd204b_rx is diff --git a/src/transport/octets_to_sample.vhd b/src/transport/octets_to_sample.vhd index 7621426..0799049 100644 --- a/src/transport/octets_to_sample.vhd +++ b/src/transport/octets_to_sample.vhd @@ -1,9 +1,18 @@ +------------------------------------------------------------------------------- +-- Title : octets to samples mapping +------------------------------------------------------------------------------- +-- File : octets_to_sample.vhd +------------------------------------------------------------------------------- +-- Description: Maps octets from lanes from data link to samples. +-- In case of any error in the data, last frame will be streamed again. +-- The data from wrong frame will be dropped. +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; use work.transport_pkg.all; - entity octets_to_samples is generic ( CS : integer := 1; -- Number of control bits per sample @@ -16,13 +25,14 @@ entity octets_to_samples is Nn : integer := 16); -- Size of a word (sample + ctrl if CF -- =0 port ( - ci_char_clk : in std_logic; - ci_frame_clk : in std_logic; - ci_reset : in std_logic; - di_lanes_data : in frame_character_array(0 to L-1); + ci_char_clk : in std_logic; -- Character clock + ci_frame_clk : in std_logic; -- Frame clock + ci_reset : in std_logic; -- Reset (asynchronous, active low) + di_lanes_data : in frame_character_array(0 to L-1); -- Data from the lanes -- bits - co_correct_data : out std_logic; - do_samples_data : out samples_array(0 to M - 1, 0 to S - 1)); + co_correct_data : out std_logic; -- Whether output is correct + do_samples_data : out samples_array(0 to M - 1, 0 to S - 1)); -- The + -- output samples end entity octets_to_samples; architecture a1 of octets_to_samples is @@ -92,6 +102,9 @@ begin -- architecture a buffered_data <= current_buffered_data or reg_buffered_data; + -- for one or multiple lanes if CF = 0 + -- (no control words) + -- (control chars are right after sample) multi_lane_no_cf: if CF = 0 generate converters: for ci in 0 to M - 1 generate samples: for si in 0 to S - 1 generate @@ -104,6 +117,8 @@ begin -- architecture a end generate converters; end generate multi_lane_no_cf; + -- for one or mutliple lanes if CF != 0 + -- (control words are present) multi_lane_cf: if CF > 0 generate cf_groups: for cfi in 0 to CF-1 generate converters: for ci in 0 to M/CF-1 generate diff --git a/src/transport/transport_layer.vhd b/src/transport/transport_layer.vhd index f13a206..ebbd28b 100644 --- a/src/transport/transport_layer.vhd +++ b/src/transport/transport_layer.vhd @@ -1,3 +1,12 @@ +------------------------------------------------------------------------------- +-- Title : transport layer +------------------------------------------------------------------------------- +-- File : transport_layer.vhd +------------------------------------------------------------------------------- +-- Description: Takes aligned frame characters from multiple lanes +-- Outputs samples from one frame by converter. +------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; @@ -15,18 +24,22 @@ entity transport_layer is Nn : integer := 16); -- Size of a word (sample + ctrl if CF -- =0 port ( - ci_char_clk : in std_logic; - ci_frame_clk : in std_logic; - ci_reset : in std_logic; - di_lanes_data : in frame_character_array(0 to L - 1); + ci_char_clk : in std_logic; -- Character clock + ci_frame_clk : in std_logic; -- Frame clock + ci_reset : in std_logic; -- Reset (asynchronous, active low) + di_lanes_data : in frame_character_array(0 to L - 1); -- Data from the lanes - co_correct_data : out std_logic; - do_samples_data : out samples_array(0 to M - 1, 0 to S - 1)); + co_correct_data : out std_logic; -- Whether the current data are correct + -- user data + do_samples_data : out samples_array(0 to M - 1, 0 to S - 1)); -- Samples + -- in the + -- given frame end entity transport_layer; architecture a1 of transport_layer is begin -- architecture a1 + -- maps data from lanes to samples octets_to_samples: entity work.octets_to_samples generic map ( CS => CS, diff --git a/src/transport/transport_pkg.vhd b/src/transport/transport_pkg.vhd index 536c782..0d9d354 100644 --- a/src/transport/transport_pkg.vhd +++ b/src/transport/transport_pkg.vhd @@ -2,14 +2,19 @@ library ieee; use ieee.std_logic_1164.all; use work.data_link_pkg.all; +-- Package for transport layer types package transport_pkg is + -- Output sample with control bits type sample is record data : std_logic_vector; ctrl_bits : std_logic_vector; end record sample; + -- Array of frame characters (characters in one frame) type frame_character_array is array (natural range <>) of frame_character; + + -- Array of samples in one frame by converter and by sample (used with oversampling) type samples_array is array (natural range <>, natural range <>) of sample; end package transport_pkg; -- 2.48.1