M src/data_link/data_link_layer.vhd => src/data_link/data_link_layer.vhd +17 -12
@@ 22,22 22,26 @@ use work.transport_pkg.all;
entity data_link_layer is
generic (
- K_character : std_logic_vector(7 downto 0) := "10111100"; -- K sync character
- R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS
+ K_character : std_logic_vector(7 downto 0) := "10111100"; -- K sync character
+ R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS
-- multiframe start
- A_character : std_logic_vector(7 downto 0) := "01111100"; -- multiframe end
- Q_character : std_logic_vector(7 downto 0) := "10011100"; -- 2nd ILAS frame
+ A_character : std_logic_vector(7 downto 0) := "01111100"; -- multiframe end
+ Q_character : std_logic_vector(7 downto 0) := "10011100"; -- 2nd ILAS frame
-- 2nd character
- ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5); -- Configuration
+ ALIGN_BUFFER_SIZE : integer := 255; -- Size of a
+ -- buffer that is
+ -- used for
+ -- aligning lanes
+ ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5); -- Configuration
-- for the error
- SCRAMBLING : std_logic := '0'; -- Whether scrambling is enabled
- SUBCLASSV : integer range 0 to 1 := 0;
- F : integer range 1 to 256 := 2; -- Number of octets in a frame
- K : integer range 1 to 32 := 1); -- Number of frames in a mutliframe
+ SCRAMBLING : std_logic := '0'; -- Whether scrambling is enabled
+ SUBCLASSV : integer range 0 to 1 := 0;
+ F : integer range 1 to 256 := 2; -- Number of octets in a frame
+ K : integer range 1 to 32 := 1); -- Number of frames in a mutliframe
port (
- ci_char_clk : in std_logic; -- Character clock
- ci_frame_clk : in std_logic; -- Frame clock
- ci_reset : in std_logic; -- Reset (asynchronous, active low)
+ ci_char_clk : in std_logic; -- Character clock
+ ci_frame_clk : in std_logic; -- Frame clock
+ ci_reset : in std_logic; -- Reset (asynchronous, active low)
-- link configuration
do_lane_config : out link_config; -- Configuration of the link
@@ 157,6 161,7 @@ begin -- architecture a1
-- lane alignment
lane_alignment : entity work.lane_alignment
generic map (
+ BUFFER_SIZE => ALIGN_BUFFER_SIZE,
F => F,
K => K)
port map (
M src/data_link/lane_alignment.vhd => src/data_link/lane_alignment.vhd +8 -8
@@ 17,7 17,7 @@ entity lane_alignment is
generic (
F : integer range 1 to 256; -- Number of octets in a frame
K : integer range 1 to 32; -- Number of frames in a multiframe
- buffer_size : integer := 256; -- How many octets to keep
+ BUFFER_SIZE : integer := 256; -- How many octets to keep
R_character : std_logic_vector(7 downto 0) := "00011100"; -- The /R/ character
dummy_character : character_vector := ('1', '0', '0', "10111100", '0'));
-- Character to send before the buffer is ready and started
@@ 42,18 42,18 @@ entity lane_alignment is
end entity lane_alignment;
architecture a1 of lane_alignment is
- type buffer_array is array (0 to buffer_size) of character_vector;
+ type buffer_array is array (0 to BUFFER_SIZE) of character_vector;
signal buff : buffer_array := (others => ('0', '0', '0', "00000000", '0'));
signal reg_ready : std_logic := '0';
signal reg_started : std_logic := '0';
signal reg_error : std_logic := '0';
- signal reg_write_index : integer range 0 to buffer_size := 0;
- signal reg_read_index : integer range 0 to buffer_size := 0;
+ signal reg_write_index : integer range 0 to BUFFER_SIZE := 0;
+ signal reg_read_index : integer range 0 to BUFFER_SIZE := 0;
- signal next_write_index : integer range 0 to buffer_size-1 := 0;
- signal next_read_index : integer range 0 to buffer_size-1 := 0;
+ signal next_write_index : integer range 0 to BUFFER_SIZE-1 := 0;
+ signal next_read_index : integer range 0 to BUFFER_SIZE-1 := 0;
signal next_ready : std_logic := '0';
signal next_started : std_logic := '0';
signal next_error : std_logic := '0';
@@ 85,9 85,9 @@ begin -- architecture a1
co_error <= reg_error;
-- TODO handle realignment ?
- next_write_index <= ((reg_write_index + 1) mod buffer_size) when reg_ready = '1' or next_ready = '1' else
+ next_write_index <= ((reg_write_index + 1) mod BUFFER_SIZE) when reg_ready = '1' or next_ready = '1' else
0;
- next_read_index <= ((reg_read_index + 1) mod buffer_size) when reg_started = '1' else
+ next_read_index <= ((reg_read_index + 1) mod BUFFER_SIZE) when reg_started = '1' else
0;
next_ready <= '0' when ci_state = INIT else
M src/jesd204b_link_rx.vhd => src/jesd204b_link_rx.vhd +50 -45
@@ 15,34 15,38 @@ use work.jesd204b_pkg.all;
entity jesd204b_link_rx is
generic (
- K_character : std_logic_vector(7 downto 0) := "10111100"; -- Sync character
- R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS first
+ K_character : std_logic_vector(7 downto 0) := "10111100"; -- Sync character
+ R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS first
-- frame character
- A_character : std_logic_vector(7 downto 0) := "01111100"; -- Multiframe
+ A_character : std_logic_vector(7 downto 0) := "01111100"; -- Multiframe
-- alignment character
- Q_character : std_logic_vector(7 downto 0) := "10011100"; -- ILAS 2nd
+ Q_character : std_logic_vector(7 downto 0) := "10011100"; -- ILAS 2nd
-- frame 2nd character
- ADJCNT : integer range 0 to 15 := 0;
- ADJDIR : std_logic := '0';
- BID : integer range 0 to 15 := 0;
- DID : integer range 0 to 255 := 0;
- HD : std_logic := '0';
- JESDV : integer range 0 to 7 := 1;
- PHADJ : std_logic := '0';
- SUBCLASSV : integer range 0 to 7 := 0;
- K : integer range 1 to 32; -- Number of frames in a
- -- multiframe
- CS : integer range 0 to 3; -- Number of control bits per sample
- M : integer range 1 to 256; -- Number of converters
- S : integer range 1 to 32; -- Number of samples
- L : integer range 1 to 32; -- Number of lanes
- F : integer range 1 to 256; -- Number of octets in a frame
- CF : integer range 0 to 32; -- Number of control words
- N : integer range 1 to 32; -- Size of a sample
- Nn : integer range 1 to 32; -- Size of a word (sample + ctrl if CF
- RX_BUFFER_DELAY : integer range 1 to 32 := 1;
- ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5);
- SCRAMBLING : std_logic := '0');
+ ADJCNT : integer range 0 to 15 := 0;
+ ADJDIR : std_logic := '0';
+ BID : integer range 0 to 15 := 0;
+ DID : integer range 0 to 255 := 0;
+ HD : std_logic := '0';
+ JESDV : integer range 0 to 7 := 1;
+ PHADJ : std_logic := '0';
+ SUBCLASSV : integer range 0 to 7 := 0;
+ K : integer range 1 to 32; -- Number of frames in a
+ -- multiframe
+ CS : integer range 0 to 3; -- Number of control bits per sample
+ M : integer range 1 to 256; -- Number of converters
+ S : integer range 1 to 32; -- Number of samples
+ L : integer range 1 to 32; -- Number of lanes
+ F : integer range 1 to 256; -- Number of octets in a frame
+ CF : integer range 0 to 32; -- Number of control words
+ N : integer range 1 to 32; -- Size of a sample
+ Nn : integer range 1 to 32; -- Size of a word (sample + ctrl if CF
+ ALIGN_BUFFER_SIZE : integer := 255; -- Size of a
+ -- buffer that is
+ -- used for
+ -- aligning lanes
+ RX_BUFFER_DELAY : integer range 1 to 32 := 1;
+ ERROR_CONFIG : error_handling_config := (2, 0, 5, 5, 5);
+ SCRAMBLING : std_logic := '0');
port (
ci_char_clk : in std_logic; -- Character clock
ci_frame_clk : in std_logic; -- Frame clock
@@ 204,27 208,28 @@ begin -- architecture a1
data_links : for i in 0 to L-1 generate
data_link_layer : entity work.data_link_layer
generic map (
- K_character => K_character,
- R_character => R_character,
- A_character => A_character,
- Q_character => Q_character,
- ERROR_CONFIG => ERROR_CONFIG,
- SCRAMBLING => SCRAMBLING,
- SUBCLASSV => SUBCLASSV,
- F => F,
- K => K)
+ ALIGN_BUFFER_SIZE => ALIGN_BUFFER_SIZE,
+ K_character => K_character,
+ R_character => R_character,
+ A_character => A_character,
+ Q_character => Q_character,
+ ERROR_CONFIG => ERROR_CONFIG,
+ SCRAMBLING => SCRAMBLING,
+ SUBCLASSV => SUBCLASSV,
+ F => F,
+ K => K)
port map (
- ci_char_clk => ci_char_clk,
- ci_frame_clk => ci_frame_clk,
- ci_reset => ci_reset,
- do_lane_config => lane_configuration_array(i),
- co_lane_ready => data_link_ready_vector(i),
- ci_lane_start => data_link_start,
- ci_request_sync => request_sync,
- co_synced => data_link_synced_vector(i),
- di_10b => di_transceiver_data(i),
- do_aligned_chars => data_link_aligned_chars_array(i),
- co_frame_state => data_link_frame_state_array(i));
+ ci_char_clk => ci_char_clk,
+ ci_frame_clk => ci_frame_clk,
+ ci_reset => ci_reset,
+ do_lane_config => lane_configuration_array(i),
+ co_lane_ready => data_link_ready_vector(i),
+ ci_lane_start => data_link_start,
+ ci_request_sync => request_sync,
+ co_synced => data_link_synced_vector(i),
+ di_10b => di_transceiver_data(i),
+ do_aligned_chars => data_link_aligned_chars_array(i),
+ co_frame_state => data_link_frame_state_array(i));
descrambler_gen: if SCRAMBLING = '1' generate
descrambler: entity work.descrambler
M src/jesd204b_multipoint_link_rx.vhd => src/jesd204b_multipoint_link_rx.vhd +31 -26
@@ 17,6 17,10 @@ entity jesd204b_multipoint_link_rx is
-- frame 2nd character
MULTIFRAME_RATE : integer; -- F * K, should be the same for every
-- device
+ ALIGN_BUFFER_SIZE : integer := 255; -- Size of a
+ -- buffer that is
+ -- used for
+ -- aligning lanes
RX_BUFFER_DELAY : integer range 1 to 32 := 1;
LINKS : integer; -- Count of links
LANES : integer; -- Total nubmer of lanes
@@ 139,32 143,33 @@ begin -- architecture a1
co_aligned => multiframe_aligned,
co_multiframe_clk => multiframe_clk);
- links_rx: for i in 0 to LINKS - 1 generate
- link: entity work.jesd204b_link_rx
+ links_rx : for i in 0 to LINKS - 1 generate
+ link : entity work.jesd204b_link_rx
generic map (
- K_character => K_character,
- R_character => R_character,
- A_character => A_character,
- Q_character => Q_character,
- ERROR_CONFIG => ERROR_CONFIG,
- RX_BUFFER_DELAY => RX_BUFFER_DELAY,
- ADJCNT => CONFIG(i).ADJCNT,
- BID => CONFIG(i).BID,
- DID => CONFIG(i).DID,
- HD => CONFIG(i).HD,
- JESDV => CONFIG(i).JESDV,
- PHADJ => CONFIG(i).PHADJ,
- SUBCLASSV => CONFIG(i).SUBCLASSV,
- K => CONFIG(i).K,
- CS => CONFIG(i).CS,
- M => CONFIG(i).M,
- S => CONFIG(i).S,
- L => CONFIG(i).L,
- F => CONFIG(i).F,
- CF => CONFIG(i).CF,
- N => CONFIG(i).N,
- Nn => CONFIG(i).Nn,
- ADJDIR => CONFIG(i).ADJDIR)
+ K_character => K_character,
+ R_character => R_character,
+ A_character => A_character,
+ Q_character => Q_character,
+ ERROR_CONFIG => ERROR_CONFIG,
+ ALIGN_BUFFER_SIZE => ALIGN_BUFFER_SIZE,
+ RX_BUFFER_DELAY => RX_BUFFER_DELAY,
+ ADJCNT => CONFIG(i).ADJCNT,
+ BID => CONFIG(i).BID,
+ DID => CONFIG(i).DID,
+ HD => CONFIG(i).HD,
+ JESDV => CONFIG(i).JESDV,
+ PHADJ => CONFIG(i).PHADJ,
+ SUBCLASSV => CONFIG(i).SUBCLASSV,
+ K => CONFIG(i).K,
+ CS => CONFIG(i).CS,
+ M => CONFIG(i).M,
+ S => CONFIG(i).S,
+ L => CONFIG(i).L,
+ F => CONFIG(i).F,
+ CF => CONFIG(i).CF,
+ N => CONFIG(i).N,
+ Nn => CONFIG(i).Nn,
+ ADJDIR => CONFIG(i).ADJDIR)
port map (
ci_char_clk => ci_char_clk,
ci_frame_clk => ci_frame_clk,
@@ 174,7 179,7 @@ begin -- architecture a1
co_nsynced => links_nsynced(i),
co_error => links_error(i),
di_transceiver_data => di_transceiver_data(sumCummulativeLanes(i) to sumCummulativeLanes(i) + CONFIG(i).L - 1),
- do_samples => do_samples(i), -- do_samples(sumCummulativeConverters(i) to sumCummulativeConverters(i) + CONFIG(i).M - 1),
+ do_samples => do_samples(i), -- do_samples(sumCummulativeConverters(i) to sumCummulativeConverters(i) + CONFIG(i).M - 1),
co_frame_state => co_frame_state(i),
co_correct_data => links_correct_data(i));
end generate links_rx;