From 3a90bcd770ae8006024ec819086cc74d972c2054 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sat, 1 Apr 2023 10:43:17 +0200 Subject: [PATCH] feat: make sync aligned to frame clock Resolves #21 --- src/data_link/data_link_layer.vhd | 1 + src/data_link/link_controller.vhd | 11 ++++++++- testbench/data_link/link_controller_tb.vhd | 28 ++++++++++++++-------- 3 files changed, 29 insertions(+), 11 deletions(-) diff --git a/src/data_link/data_link_layer.vhd b/src/data_link/data_link_layer.vhd index e56f71a..39696fd 100644 --- a/src/data_link/data_link_layer.vhd +++ b/src/data_link/data_link_layer.vhd @@ -120,6 +120,7 @@ begin -- architecture a1 F => F, K => K) port map ( + ci_frame_clk => ci_frame_clk, ci_char_clk => ci_char_clk, ci_reset => ci_reset, ci_resync => link_controller_ci_resync, diff --git a/src/data_link/link_controller.vhd b/src/data_link/link_controller.vhd index dfe894c..0a2a31c 100644 --- a/src/data_link/link_controller.vhd +++ b/src/data_link/link_controller.vhd @@ -24,6 +24,7 @@ entity link_controller is K : integer; -- Number of frames in a multiframe K_character : std_logic_vector(7 downto 0) := "10111100"); -- Sync character port ( + ci_frame_clk : in std_logic; -- Frame clock ci_char_clk : in std_logic; -- Character clock ci_reset : in std_logic; -- Reset (asynchronous, active low) di_char : in character_vector; -- Output character from 8b10b decoder @@ -117,7 +118,15 @@ begin -- architecture a1 end if; end process set_state; - co_synced <= synced; + set_synced: process(ci_frame_clk, ci_reset) is + begin + if ci_reset = '0' then + co_synced <= '0'; + elsif ci_frame_clk'event and ci_frame_clk = '1' then + co_synced <= synced; + end if; + end process set_synced; + synced <= '0' when reg_state = INIT or (reg_state = CGS and reg_k_counter < SYNC_COUNT) else '1'; co_state <= reg_state; diff --git a/testbench/data_link/link_controller_tb.vhd b/testbench/data_link/link_controller_tb.vhd index 12dbcd8..25c3eee 100644 --- a/testbench/data_link/link_controller_tb.vhd +++ b/testbench/data_link/link_controller_tb.vhd @@ -187,12 +187,14 @@ architecture a1 of link_controller_tb is (('0', '0', '0', "00000000", '0'), '0', '0', '0', '0', '0', '0', '0', INIT, '0', '0', -1) ); - constant clk_period : time := 1 ns; + constant char_clk_period : time := 1 ns; + constant frame_clk_period : time := char_clk_period * F; constant F : integer range 0 to 256 := 17; constant K : integer range 0 to 32 := 1; - signal clk : std_logic := '0'; + signal char_clk : std_logic := '0'; + signal frame_clk : std_logic := '0'; signal reset : std_logic := '0'; signal di_char : character_vector; @@ -220,7 +222,8 @@ begin -- architecture a1 F => F, K => K) port map ( - ci_char_clk => clk, + ci_frame_clk => frame_clk, + ci_char_clk => char_clk, ci_reset => reset, ci_resync => ci_resync, ci_lane_alignment_aligned => ci_lane_alignment_aligned, @@ -236,15 +239,20 @@ begin -- architecture a1 co_error => co_error ); - clk_gen: process is + char_clk_gen: process is begin -- process clk_gen - wait for clk_period/2; - clk <= not clk; - end process clk_gen; + wait for char_clk_period/2; + char_clk <= not char_clk; + end process char_clk_gen; + frame_clk_gen: process is + begin -- process clk_gen + wait for frame_clk_period/2; + frame_clk <= not clk; + end process frame_clk_gen; reset_gen: process is begin -- process reset_gen - wait for clk_period*2; + wait for char_clk_period*2; reset <= '1'; end process reset_gen; @@ -252,7 +260,7 @@ begin -- architecture a1 variable test_vec : test_vector; variable prev_test_vec : test_vector; begin -- process test - wait for clk_period*2; + wait for char_clk_period*2; for i in test_vectors'range loop test_data_index <= i; @@ -278,7 +286,7 @@ begin -- architecture a1 assert co_uncorrectable_error = prev_test_vec.expected_uncorrectable_error report "The uncorrectable error does not match. Index: " & integer'image(i-1) severity error; end if; - wait for clk_period; + wait for char_clk_period; end loop; -- i wait for 100 ms; end process test; -- 2.48.1