23 files changed, 104 insertions(+), 104 deletions(-)

M src/data_link/an8b10b_decoder.vhd
M src/data_link/char_alignment.vhd
M src/data_link/data_link_layer.vhd
M src/data_link/data_link_pkg.vhd
M src/data_link/error_handler.vhd
M src/data_link/frame_alignment.vhd
M src/data_link/ilas_parser.vhd
M src/data_link/lane_alignment.vhd
M src/data_link/link_controller.vhd
M src/jesd204b_link_rx.vhd
M src/jesd204b_multipoint_link_rx.vhd
M src/lmfc_counter.vhd
M src/lmfc_generation.vhd
M src/synced_combination.vhd
M testbench/data_link/an8b10bdecoder_tb.vhd
M testbench/data_link/frame_alignment_tb.vhd
M testbench/data_link/ilas_parser_tb.vhd
M testbench/data_link/lane_alignment_tb.vhd
M testbench/data_link/link_controller_tb.vhd
M testbench/jesd204b_multipoint_data_tb.vhd
M testbench/jesd204b_rx_data_tb.vhd
M testbench/jesd204b_rx_ils_tb.vhd
M testbench/jesd204b_rx_kchars_tb.vhd

@@ 20,7 20,7 @@ entity an8b10b_decoder is
     ci_char_clk : in  std_logic;        -- The character clock
     ci_reset    : in  std_logic;        -- The reset (asynchronous active low)
     di_10b      : in  std_logic_vector(9 downto 0);  -- The 8b10b encoded input data
-    do_char     : out character_vector;  -- The output decoded 8b data
+    do_char     : out link_character;  -- The output decoded 8b data
     co_error    : out std_logic);       -- Whether there is an error (disparity
                                         -- or missing)
 end entity an8b10b_decoder;

@@ 17,7 17,7 @@ use ieee.std_logic_1164.all;
 entity char_alignment is
 
   generic (
-    sync_char : std_logic_vector(9 downto 0) := "0011111010"  -- The character used for synchronization (positive RD)
+    K_CHAR : std_logic_vector(9 downto 0) := "0011111010"  -- The character used for synchronization (positive RD)
     );
   port (
     ci_char_clk: in std_logic;          -- The character clock


@@ 77,9 77,9 @@ begin  -- architecture a1
       -- Try to find /K/ character again and again until ci_synced is one (that
       -- will be set by 8b10b_decoder)
       if ci_synced = '0' then
-        -- Try to find /K/ (sync_char) in either RD (either sync_char or not sync_char).
+        -- Try to find /K/ (K_CHAR) in either RD (either K_CHAR or not K_CHAR).
         for i in 0 to 9 loop
-          if reg_cache_10b(i+9 downto i) = sync_char or reg_cache_10b(i+9 downto i) = not sync_char then
+          if reg_cache_10b(i+9 downto i) = K_CHAR or reg_cache_10b(i+9 downto i) = not K_CHAR then
             reg_found_sync_char <= '1';
             reg_alignment_index <= i;
           end if;

@@ 22,11 22,11 @@ use work.transport_pkg.all;
 
 entity data_link_layer is
   generic (
-    K_character       : std_logic_vector(7 downto 0) := "10111100";  -- K sync character
-    R_character       : std_logic_vector(7 downto 0) := "00011100";  -- ILAS
+    K_CHAR       : std_logic_vector(7 downto 0) := "10111100";  -- K sync character
+    R_CHAR       : std_logic_vector(7 downto 0) := "00011100";  -- ILAS
                                         -- multiframe start
-    A_character       : std_logic_vector(7 downto 0) := "01111100";  -- multiframe end
-    Q_character       : std_logic_vector(7 downto 0) := "10011100";  -- 2nd ILAS frame
+    A_CHAR       : std_logic_vector(7 downto 0) := "01111100";  -- multiframe end
+    Q_CHAR       : std_logic_vector(7 downto 0) := "10011100";  -- 2nd ILAS frame
                                         -- 2nd character
     ALIGN_BUFFER_SIZE : integer                      := 255;  -- Size of a
                                                               -- buffer that is


@@ 61,7 61,7 @@ end entity data_link_layer;
 architecture a1 of data_link_layer is
   signal char_alignment_do_10b : std_logic_vector(9 downto 0);
 
-  signal decoder_do_char : character_vector;
+  signal decoder_do_char : link_character;
 
   signal error_handler_co_request_sync : std_logic;
 


@@ 69,7 69,7 @@ architecture a1 of data_link_layer is
   signal lane_alignment_co_aligned            : std_logic;
   signal lane_alignment_co_error              : std_logic;
   signal lane_alignment_co_ready              : std_logic;
-  signal lane_alignment_do_char               : character_vector;
+  signal lane_alignment_do_char               : link_character;
   signal lane_alignment_co_correct_sync_chars : integer;
 
   signal frame_alignment_ci_request_sync       : std_logic;

@@ 3,14 3,14 @@ use ieee.std_logic_1164.all;
 
 package data_link_pkg is
 
-  type character_vector is record
+  type link_character is record
     kout            : std_logic;  -- Whether the character is a control character
     disparity_error : std_logic;  -- Whether there was a disparity error (if this is true, the character will still be correct)
     missing_error   : std_logic;  -- Whether the character was not found in the table
     d8b             : std_logic_vector(7 downto 0);  -- The decoded data
     user_data      : std_logic;         -- Whether the data is user data (in
                                         -- DATA state, false otherwise)
-  end record character_vector;
+  end record link_character;
 
   type frame_character is record
     kout            : std_logic;  -- Whether the character is a control character

@@ 23,7 23,7 @@ entity error_handler is
                                                        -- active low)
     ci_state                         : in link_state;  -- State of the lane.
 
-    di_char                          : in  character_vector;  -- Character from
+    di_char                          : in  link_character;  -- Character from
                                                               -- 8b10b decoder
 
     ci_lane_alignment_error          : in  std_logic;  -- Signals an error with

@@ 22,17 22,17 @@ entity frame_alignment is
     SCRAMBLING : std_logic; -- Whether data are scrambled
     F : integer range 0 to 256 := 8; -- Number of octets in a frame
     K : integer range 0 to 32 := 1; -- Number of frames in a multiframe
-    sync_char      : std_logic_vector(7 downto 0) := "10111100";  -- K
+    K_CHAR      : std_logic_vector(7 downto 0) := "10111100";  -- K
                                                                   -- character
                                                                   -- for syncing
-    A_char         : std_logic_vector(7 downto 0) := "01111100";  -- Last
+    A_CHAR         : std_logic_vector(7 downto 0) := "01111100";  -- Last
                                                                   -- character
                                                                   -- in multiframe
-    F_char         : std_logic_vector(7 downto 0) := "11111100";  -- Last
+    F_CHAR         : std_logic_vector(7 downto 0) := "11111100";  -- Last
                                                                   -- character
                                                                   -- in frame
-    F_replace_data : std_logic_vector(7 downto 0) := "11111100";  -- The character to replace with upon receiving /F/ with scrambled data
-    A_replace_data : std_logic_vector(7 downto 0) := "01111100");  -- The character to replace with upon receiving /A/ with scrambled data
+    F_REPLACE_CHAR : std_logic_vector(7 downto 0) := "11111100";  -- The character to replace with upon receiving /F/ with scrambled data
+    A_REPLACE_CHAR : std_logic_vector(7 downto 0) := "01111100");  -- The character to replace with upon receiving /A/ with scrambled data
   port (
     ci_char_clk           : in  std_logic;  -- Character clock
     ci_frame_clk          : in  std_logic;  -- Frame clock


@@ 40,7 40,7 @@ entity frame_alignment is
     ci_request_sync       : in  std_logic;  -- Whether sync is requested
     ci_realign            : in  std_logic;  -- Whether to realign to last
                                             -- alignment character
-    di_char               : in  character_vector;  -- The received character
+    di_char               : in  link_character;  -- The received character
     co_aligned            : out std_logic;  -- Whether the alignment is right
     co_error              : out std_logic;  -- Whether there was an error with
                                             -- the alignment


@@ 187,15 187,15 @@ begin  -- architecture a1
   is_wrong_char <= (is_f and not next_is_last_octet) or (is_a and not next_is_last_octet);
   buffer_character <= di_char.d8b when is_f = '0' and is_a = '0' else
                  reg_last_frame_data when SCRAMBLING = '0' else
-                 F_replace_data when is_f = '1' else
-                 A_replace_data;
+                 F_REPLACE_CHAR when is_f = '1' else
+                 A_REPLACE_CHAR;
 
   next_adjusted_octet_index <= (buffer_write_position - buffer_read_position - buffer_adjust_position) mod F;
   next_octet_index <= (buffer_write_position - buffer_read_position) mod F;
   next_is_last_octet <= '1' when next_adjusted_octet_index = F - 1 else '0';
 
-  is_f <= '1' when di_char.d8b = F_char and di_char.kout = '1' else '0';
-  is_a <= '1' when di_char.d8b = A_char and di_char.kout = '1' else '0';
+  is_f <= '1' when di_char.d8b = F_CHAR and di_char.kout = '1' else '0';
+  is_a <= '1' when di_char.d8b = A_CHAR and di_char.kout = '1' else '0';
 
   co_error <= '1' when reg_state = MISALIGNED else '0';
   co_aligned <= '1' when reg_state = ALIGNED else '0';

@@ 16,24 16,23 @@ entity ilas_parser is
   generic (
     F                 : integer range 1 to 256;  -- Number of octets in a frame
     K                 : integer range 1 to 32;  -- Number of frames in a multiframe
-    K_character       : std_logic_vector(7 downto 0) := "10111100";  -- Character
+    K_CHAR       : std_logic_vector(7 downto 0) := "10111100";  -- Character
                                         -- for syncing
-    R_character       : std_logic_vector(7 downto 0) := "00011100";  -- ILAS
+    R_CHAR       : std_logic_vector(7 downto 0) := "00011100";  -- ILAS
                                         -- multiframe
                                         -- start character
-    A_character       : std_logic_vector(7 downto 0) := "01111100";  -- ILAS
+    A_CHAR       : std_logic_vector(7 downto 0) := "01111100";  -- ILAS
                                         -- multiframe
                                         -- end character
-    Q_character       : std_logic_vector(7 downto 0) := "10011100";  -- ILAS 2nd
+    Q_CHAR       : std_logic_vector(7 downto 0) := "10011100");  -- ILAS 2nd
                                         -- multiframe
                                         -- 2nd character
-    multiframes_count : integer range 1 to 32        := 4);
 
   port (
     ci_char_clk        : in  std_logic;  -- Character clock
     ci_reset           : in  std_logic;  -- Reset (asynchonous, active low)
     ci_state           : in  link_state;  -- State of the lane
-    di_char            : in  character_vector;  -- Character from 8b10b decoder
+    di_char            : in  link_character;  -- Character from 8b10b decoder
     do_config          : out link_config;  -- Config found in ILAS
     co_finished        : out std_logic;  -- The ILAS was received correctly
     co_error           : out std_logic;  -- The ILAS was not received correctly


@@ 44,6 43,7 @@ entity ilas_parser is
 end entity ilas_parser;
 
 architecture a1 of ilas_parser is
+  constant multiframes_count : integer := 4;
   constant link_config_length : integer := 112;
   signal octets_in_multiframe : integer range 0 to 8192 := 0;
   signal link_config_data : std_logic_vector(link_config_length-1 downto 0) := (others => '0');


@@ 146,25 146,25 @@ begin  -- architecture a1
       -- If there is an error, stop processing.
     elsif ci_char_clk'event and ci_char_clk = '1' and processing_ilas = '1' then  -- rising clock edge
       if reg_octet_index = 0 then       -- Should be /R/
-        if di_char.d8b /= R_character or di_char.kout = '0' then
+        if di_char.d8b /= R_CHAR or di_char.kout = '0' then
           err <= '1';
           co_unexpected_char <= '1';
         end if;
-      elsif di_char.d8b = R_character and di_char.kout = '1' then
+      elsif di_char.d8b = R_CHAR and di_char.kout = '1' then
         err <= '1';
         co_unexpected_char <= '1';
       elsif reg_octet_index = octets_in_multiframe - 1 then
-        if di_char.d8b /= A_character or di_char.kout = '0' then  -- Should be /A/
+        if di_char.d8b /= A_CHAR or di_char.kout = '0' then  -- Should be /A/
           err <= '1';
           co_unexpected_char <= '1';
         elsif reg_multiframe_index = 3 and err = '0' then
           finished <= '1';
         end if;
-      elsif di_char.d8b = A_character and di_char.kout = '1' then
+      elsif di_char.d8b = A_CHAR and di_char.kout = '1' then
         err <= '1';
         co_unexpected_char <= '1';
       elsif reg_multiframe_index = 1 then
-        if reg_octet_index = 1 and (di_char.d8b /= Q_character or di_char.kout = '0') then  -- Should be /Q/
+        if reg_octet_index = 1 and (di_char.d8b /= Q_CHAR or di_char.kout = '0') then  -- Should be /Q/
           err <= '1';
           co_unexpected_char <= '1';
         elsif reg_octet_index > 1 and reg_octet_index < 16 then    -- This is config data


@@ 186,13 186,13 @@ begin  -- architecture a1
     end if;
   end process check_chars;
 
-  co_finished <= '1' when finished = '1' or (di_char.kout = '1' and di_char.d8b = A_character and reg_octet_index = octets_in_multiframe - 1 and reg_multiframe_index = 3) else '0';
+  co_finished <= '1' when finished = '1' or (di_char.kout = '1' and di_char.d8b = A_CHAR and reg_octet_index = octets_in_multiframe - 1 and reg_multiframe_index = 3) else '0';
   co_error <= '1' when err = '1' and ci_state = ILS else '0';
 
   next_processing_ilas <= '0' when ci_state = INIT or finished = '1' else
                           '0' when ci_state = CGS and reg_processing_ilas = '1' else
                           '0' when reg_multiframe_index = 3 and reg_octet_index = octets_in_multiframe - 1 else
-                          '1' when ci_state = CGS and not (di_char.d8b = K_character and di_char.kout = '1') else
+                          '1' when ci_state = CGS and not (di_char.d8b = K_CHAR and di_char.kout = '1') else
                           '1' when reg_processing_ilas = '1' or ci_state = ILS else
                           '0';
 

@@ 18,8 18,8 @@ entity lane_alignment is
     F               : integer range 1 to 256;  -- Number of octets in a frame
     K               : integer range 1 to 32;  -- Number of frames in a multiframe
     BUFFER_SIZE     : integer                      := 256;  -- How many octets to keep
-    R_character     : std_logic_vector(7 downto 0) := "00011100";  -- The /R/ character
-    dummy_character : character_vector             := ('1', '0', '0', "10111100", '0'));
+    R_CHAR     : std_logic_vector(7 downto 0) := "00011100";  -- The /R/ character
+    DUMMY_CHAR : link_character             := ('1', '0', '0', "10111100", '0'));
 -- Character to send before the buffer is ready and started
 
   port (


@@ 30,19 30,19 @@ entity lane_alignment is
     ci_state              : in  link_state;  -- State of the lane
     ci_realign            : in  std_logic;  -- Whether to realign to the last
                                             -- found alignment character
-    di_char               : in  character_vector;  -- Character from 8b10b decoder
+    di_char               : in  link_character;  -- Character from 8b10b decoder
     co_ready              : out std_logic;  -- Whether /A/ was received and
                                             -- waiting for start
     co_aligned            : out std_logic;  -- Whether the alignment is still correct
     co_correct_sync_chars : out integer;  -- How many alignment characters on
                                           -- correct place were found in a row
     co_error              : out std_logic;  -- Whether there is an error
-    do_char               : out character_vector);  -- The aligned output character
+    do_char               : out link_character);  -- The aligned output character
 
 end entity lane_alignment;
 
 architecture a1 of lane_alignment is
-  type buffer_array is array (0 to BUFFER_SIZE) of character_vector;
+  type buffer_array is array (0 to BUFFER_SIZE) of link_character;
   signal buff : buffer_array := (others => ('0', '0', '0', "00000000", '0'));
 
   signal reg_ready : std_logic := '0';


@@ 91,7 91,7 @@ begin  -- architecture a1
                      0;
 
   next_ready <= '0' when ci_state = INIT else
-                '1' when reg_ready = '1' or (di_char.kout = '1' and di_char.d8b = R_character and (ci_state = CGS or ci_state = ILS)) else
+                '1' when reg_ready = '1' or (di_char.kout = '1' and di_char.d8b = R_CHAR and (ci_state = CGS or ci_state = ILS)) else
                 '0';
   next_started <= '0' when reg_ready = '0' or ci_state = CGS else
                   '1' when (ci_start = '1' or reg_started = '1') else


@@ 102,7 102,7 @@ begin  -- architecture a1
                 '1' when reg_ready = '1' and reg_started = '0' and (reg_write_index = 0) else
                 '0';
 
-  do_char <= dummy_character when ci_state = INIT or reg_started = '0' else
+  do_char <= DUMMY_CHAR when ci_state = INIT or reg_started = '0' else
              buff(reg_read_index);
 
 end architecture a1;

@@ 23,12 23,12 @@ entity link_controller is
     SUBCLASSV   : integer range 0 to 1 := 0;
     F           : integer range 1 to 256;     -- Number of octets in a frame
     K           : integer range 1 to 32;  -- Number of frames in a multiframe
-    K_character : std_logic_vector(7 downto 0) := "10111100");  -- Sync character
+    K_CHAR : std_logic_vector(7 downto 0) := "10111100");  -- Sync character
   port (
     ci_frame_clk      : in std_logic;   -- Frame clock
     ci_char_clk       : in std_logic;   -- Character clock
     ci_reset          : in std_logic;   -- Reset (asynchronous, active low)
-    di_char           : in character_vector;  -- Output character from 8b10b decoder
+    di_char           : in link_character;  -- Output character from 8b10b decoder
 
     do_config : out link_config;  -- Config found in ILAS
 


@@ 109,15 109,15 @@ begin  -- architecture a1
       elsif reg_state = CGS then
         if reg_k_counter < SYNC_COUNT then
           correct_8b10b_characters <= 1;
-          if di_char.d8b = K_character and di_char.kout = '1' then
+          if di_char.d8b = K_CHAR and di_char.kout = '1' then
             reg_k_counter <= reg_k_counter + 1;
           else
             reg_k_counter <= 0;
           end if;
-        elsif di_char.d8b /= K_character or di_char.kout = '0' then
+        elsif di_char.d8b /= K_CHAR or di_char.kout = '0' then
           reg_state <= ILS;
         end if;
-      elsif di_char.d8b = K_character and di_char.kout = '1' then
+      elsif di_char.d8b = K_CHAR and di_char.kout = '1' then
         reg_state <= CGS;
         reg_k_counter <= 0;
       elsif reg_state = ILS then

@@ 15,12 15,12 @@ use work.jesd204b_pkg.all;
 
 entity jesd204b_link_rx is
   generic (
-    K_character       : std_logic_vector(7 downto 0) := "10111100";  -- Sync character
-    R_character       : std_logic_vector(7 downto 0) := "00011100";  -- ILAS first
+    K_CHAR       : std_logic_vector(7 downto 0) := "10111100";  -- Sync character
+    R_CHAR       : std_logic_vector(7 downto 0) := "00011100";  -- ILAS first
                                         -- frame character
-    A_character       : std_logic_vector(7 downto 0) := "01111100";  -- Multiframe
+    A_CHAR       : std_logic_vector(7 downto 0) := "01111100";  -- Multiframe
                                         -- alignment character
-    Q_character       : std_logic_vector(7 downto 0) := "10011100";  -- ILAS 2nd
+    Q_CHAR       : std_logic_vector(7 downto 0) := "10011100";  -- ILAS 2nd
                                         -- frame 2nd character
     ADJCNT            : integer range 0 to 15        := 0;
     ADJDIR            : std_logic                    := '0';


@@ 57,7 57,7 @@ entity jesd204b_link_rx is
     co_nsynced : out std_logic;  -- Whether receiver is synced (active low)
     co_error   : out std_logic;
 
-    di_transceiver_data : in  lane_input_array(0 to L-1);  -- Data from transceivers
+    di_data : in  lane_input_array(0 to L-1);  -- Data from transceivers
     do_samples          : out samples_array(0 to M - 1, 0 to S - 1);
     co_frame_state      : out frame_state;  -- Output samples
     co_correct_data     : out std_logic);  -- Whether samples are correct user


@@ 132,7 132,7 @@ begin  -- architecture a1
     generic map (
       SUBCLASSV => SUBCLASSV,
       N         => L,
-      INVERSE   => '0')
+      INVERT   => '0')
     port map (
       ci_frame_clk      => ci_frame_clk,
       ci_multiframe_clk => ci_multiframe_clk,


@@ 194,10 194,10 @@ begin  -- architecture a1
     data_link_layer : entity work.data_link_layer
       generic map (
         ALIGN_BUFFER_SIZE => ALIGN_BUFFER_SIZE,
-        K_character       => K_character,
-        R_character       => R_character,
-        A_character       => A_character,
-        Q_character       => Q_character,
+        K_CHAR       => K_CHAR,
+        R_CHAR       => R_CHAR,
+        A_CHAR       => A_CHAR,
+        Q_CHAR       => Q_CHAR,
         ERROR_CONFIG      => ERROR_CONFIG,
         SCRAMBLING        => SCRAMBLING,
         SUBCLASSV         => SUBCLASSV,


@@ 212,7 212,7 @@ begin  -- architecture a1
         ci_lane_start    => data_link_start,
         ci_request_sync  => request_sync,
         co_synced        => data_link_synced_vector(i),
-        di_10b           => di_transceiver_data(i),
+        di_10b           => di_data(i),
         do_aligned_chars => data_link_aligned_chars_array(i),
         co_frame_state   => data_link_frame_state_array(i));
 

@@ 7,13 7,13 @@ use work.transport_pkg.all;
 entity jesd204b_multipoint_link_rx is
 
   generic (
-    K_character          : std_logic_vector(7 downto 0) := "10111100";  -- Sync character
-    R_character          : std_logic_vector(7 downto 0) := "00011100";  -- ILAS first
+    K_CHAR          : std_logic_vector(7 downto 0) := "10111100";  -- Sync character
+    R_CHAR          : std_logic_vector(7 downto 0) := "00011100";  -- ILAS first
                                         -- frame character
-    A_character          : std_logic_vector(7 downto 0) := "01111100";  -- Multiframe
+    A_CHAR          : std_logic_vector(7 downto 0) := "01111100";  -- Multiframe
                                         -- alignment character
-    Q_character          : std_logic_vector(7 downto 0) := "10011100";  -- ILAS 2nd
-    DATA_RATE_MULT       : integer;  -- DEVICE_CLK_FREQ*this is lane bit rate
+    Q_CHAR          : std_logic_vector(7 downto 0) := "10011100";  -- ILAS 2nd
+    DATA_RATE       : integer;  -- DEVICE_CLK_FREQ*this is lane bit rate
                                      -- frame 2nd character
     MULTIFRAME_RATE      : integer;     -- F * K, should be the same for every
                                         -- device


@@ 37,7 37,7 @@ entity jesd204b_multipoint_link_rx is
     ci_request_sync     : in  std_logic;
     co_nsynced          : out std_logic;
     co_error            : out std_logic;
-    di_transceiver_data : in  lane_input_array(0 to LANES - 1);
+    di_data : in  lane_input_array(0 to LANES - 1);
     do_samples          : out simple_samples_array(0 to LINKS - 1)(0 to CONFIG(0).M - 1, 0 to CONFIG(0).CS - 1);
     co_frame_state      : out frame_state_array(0 to LINKS - 1);
     co_correct_data     : out std_logic);


@@ 94,7 94,7 @@ begin  -- architecture a1
     generic map (
       SUBCLASSV => CONFIG(0).SUBCLASSV,
       N         => LINKS,
-      INVERSE   => '1')
+      INVERT   => '1')
     port map (
       ci_frame_clk      => ci_frame_clk,
       ci_multiframe_clk => multiframe_clk,


@@ 106,7 106,7 @@ begin  -- architecture a1
   lmfc_generation: entity work.lmfc_generation
     generic map (
       MULTIFRAME_RATE => MULTIFRAME_RATE,
-      DATA_RATE_MULT  => DATA_RATE_MULT)
+      DATA_RATE  => DATA_RATE)
     port map (
       ci_device_clk     => ci_device_clk,
       ci_reset          => ci_reset,


@@ 118,10 118,10 @@ begin  -- architecture a1
   links_rx : for i in 0 to LINKS - 1 generate
     link : entity work.jesd204b_link_rx
       generic map (
-        K_character       => K_character,
-        R_character       => R_character,
-        A_character       => A_character,
-        Q_character       => Q_character,
+        K_CHAR       => K_CHAR,
+        R_CHAR       => R_CHAR,
+        A_CHAR       => A_CHAR,
+        Q_CHAR       => Q_CHAR,
         ERROR_CONFIG      => ERROR_CONFIG,
         ALIGN_BUFFER_SIZE => ALIGN_BUFFER_SIZE,
         RX_BUFFER_DELAY   => RX_BUFFER_DELAY,


@@ 150,7 150,7 @@ begin  -- architecture a1
       ci_request_sync     => ci_request_sync,
       co_nsynced          => links_nsynced(i),
       co_error            => links_error(i),
-      di_transceiver_data => di_transceiver_data(sumCummulativeLanes(i) to sumCummulativeLanes(i) + CONFIG(i).L - 1),
+      di_data => di_data(sumCummulativeLanes(i) to sumCummulativeLanes(i) + CONFIG(i).L - 1),
       do_samples          => do_samples(i),  -- do_samples(sumCummulativeConverters(i) to sumCummulativeConverters(i) + CONFIG(i).M - 1),
       co_frame_state      => co_frame_state(i),
       co_correct_data     => links_correct_data(i));

@@ 4,7 4,7 @@ use ieee.std_logic_1164.all;
 entity lmfc_counter is
 
   generic (
-    DATA_RATE_MULT         : integer;   -- DEV_CLK_FREQ*this is the frequency
+    DATA_RATE         : integer;   -- DEV_CLK_FREQ*this is the frequency
                                         -- of data rate (bit rate)
     PHASE_ADJUST           : integer;   -- How many more clock cycles to wait
                                         -- after sysref until lmfc ticks


@@ 21,7 21,7 @@ entity lmfc_counter is
 end entity lmfc_counter;
 
 architecture a1 of lmfc_counter is
-  constant COUNT_TO : integer := MULTIFRAME_RATE/(DATA_RATE_MULT/10);
+  constant COUNT_TO : integer := MULTIFRAME_RATE/(DATA_RATE/10);
 
   signal count : integer range 0 to COUNT_TO;
   signal prev_sysref : std_logic;

@@ 4,7 4,7 @@ use ieee.std_logic_1164.all;
 entity lmfc_generation is
   generic (
     MULTIFRAME_RATE : integer;
-    DATA_RATE_MULT  : integer);
+    DATA_RATE  : integer);
   port (
     ci_device_clk     : in  std_logic;
     ci_reset          : in  std_logic;


@@ 47,7 47,7 @@ begin  -- architecture a1
 
   multiframe_gen: entity work.lmfc_counter
   generic map (
-    DATA_RATE_MULT  => DATA_RATE_MULT,
+    DATA_RATE  => DATA_RATE,
     PHASE_ADJUST    => 0,
     MULTIFRAME_RATE => MULTIFRAME_RATE)
   port map (

@@ 6,7 6,7 @@ entity synced_combination is
   generic (
     SUBCLASSV : integer := 0;
     N : integer := 1;
-    INVERSE : std_logic := '0');
+    INVERT : std_logic := '0');
   port (
     ci_frame_clk : in std_logic;
     ci_multiframe_clk : in std_logic;


@@ 23,10 23,10 @@ architecture a1 of synced_combination is
 
   signal nsynced : std_logic;
 begin  -- architecture a1
-  gen_nsynced: if INVERSE = '0' generate
+  gen_nsynced: if INVERT = '0' generate
     nsynced <= '0' when ci_synced_array = all_ones else '1';
   end generate gen_nsynced;
-  gen_nsynced_inverse: if INVERSE = '1' generate
+  gen_nsynced_inverse: if INVERT = '1' generate
     nsynced <= '0' when ci_synced_array = all_zeros else '1';
   end generate gen_nsynced_inverse;
 

@@ 50,7 50,7 @@ architecture a1 of an8b10bdecoder_tb is
   signal co_missing_error : std_logic;
   signal co_disparity_error : std_logic;
 
-  signal char : character_vector := ('0', '0', '0', "00000000", '0');
+  signal char : link_character := ('0', '0', '0', "00000000", '0');
   signal test_data_index : integer := 0;
 begin  -- architecture a1
   uut: entity work.an8b10b_decoder

@@ 14,7 14,7 @@ architecture a1 of frame_alignment_tb is
   type test_vector is record
     ci_request_sync : std_logic;
     ci_realign : std_logic;
-    di_char : character_vector;
+    di_char : link_character;
 
     expected_aligned : std_logic;
     expected_error : std_logic;


@@ 71,7 71,7 @@ architecture a1 of frame_alignment_tb is
   signal frame_clk : std_logic := '0';
   signal reset : std_logic := '0';
 
-  signal di_char : character_vector;
+  signal di_char : link_character;
   signal do_aligned_chars : std_logic_vector(8*F - 1 downto 0);
   signal co_frame_state : frame_state;
 

@@ 9,7 9,7 @@ end entity ilas_parser_tb;
 architecture a1 of ilas_parser_tb is
   type test_vector is record
     ci_state : link_state;
-    di_char  : character_vector;
+    di_char  : link_character;
 
     expected_finished : std_logic;
     expected_error : std_logic;


@@ 237,7 237,7 @@ architecture a1 of ilas_parser_tb is
 
   signal ci_state : link_state := INIT;
 
-  signal di_char : character_vector;
+  signal di_char : link_character;
   signal do_config : link_config;
 
   signal co_finished : std_logic;

@@ 10,9 10,9 @@ architecture a1 of lane_alignment_tb is
   type test_vector is record
     ci_state : link_state;
     ci_start : std_logic;
-    di_char  : character_vector;
+    di_char  : link_character;
 
-    expected_char : character_vector;
+    expected_char : link_character;
     expected_ready : std_logic;
     expected_aligned : std_logic;
     expected_error : std_logic;


@@ 54,8 54,8 @@ architecture a1 of lane_alignment_tb is
   signal ci_start : std_logic := '0';
   signal ci_state : link_state := INIT;
 
-  signal di_char : character_vector;
-  signal do_char : character_vector;
+  signal di_char : link_character;
+  signal do_char : link_character;
 
   signal co_aligned : std_logic;
   signal co_error : std_logic;

@@ 8,7 8,7 @@ end entity link_controller_tb;
 
 architecture a1 of link_controller_tb is
   type test_vector is record
-    di_char                   : character_vector;
+    di_char                   : link_character;
     ci_resync                 : std_logic;
     ci_lane_alignment_error   : std_logic;
     ci_lane_alignment_aligned : std_logic;


@@ 201,7 201,7 @@ architecture a1 of link_controller_tb is
   signal frame_clk : std_logic := '0';
   signal reset : std_logic := '0';
 
-  signal di_char : character_vector;
+  signal di_char : link_character;
   signal do_config : link_config;
 
   signal ci_resync : std_logic := '0';

@@ 142,7 142,7 @@ architecture a1 of jesd204b_multipoint_rx_data_tb is
   constant frame_clk_period : time := 1 ns * CONFIG(0).F;    -- The clock period
   constant sysref_period : time := char_clk_period * CONFIG(0).K * CONFIG(0).F;    -- The clock period
 
-  signal di_transceiver_data : lane_input_array(0 to LANES-1);
+  signal di_data : lane_input_array(0 to LANES-1);
   signal di_lane_data : lane_data_array(0 to LANES-1);
 
   signal sysref    : std_logic := '0';


@@ 161,7 161,7 @@ architecture a1 of jesd204b_multipoint_rx_data_tb is
 begin  -- architecture a1
   uut : entity work.jesd204b_multipoint_link_rx
     generic map (
-      DATA_RATE_MULT => 10,
+      DATA_RATE => 10,
       MULTIFRAME_RATE => F*K,
       RX_BUFFER_DELAY => 6,
       LINKS      => LINKS,


@@ 175,7 175,7 @@ begin  -- architecture a1
       ci_sysref           => sysref,
       ci_reset            => reset,
       ci_request_sync     => '0',
-      di_transceiver_data => di_transceiver_data,
+      di_data => di_data,
       co_nsynced          => co_nsynced,
       co_error            => co_error,
       do_samples          => do_samples,


@@ 189,7 189,7 @@ begin  -- architecture a1
         ena     => '1',
         KI      => di_lane_data(i).k,
         datain  => di_lane_data(i).data,
-        dataout => di_transceiver_data(i));
+        dataout => di_data(i));
   end generate encoders;
 
   char_clk <= not char_clk after char_clk_period/2;

@@ 130,7 130,7 @@ architecture a1 of jesd204b_rx_data_tb is
   constant char_clk_period : time := 1 ns;    -- The clock period
   constant frame_clk_period : time := 1 ns * F;    -- The clock period
 
-  signal di_transceiver_data : lane_input_array(0 to L-1);
+  signal di_data : lane_input_array(0 to L-1);
   signal di_lane_data : lane_data_array(0 to L-1);
 
   signal char_clk : std_logic := '0';        -- The clock


@@ 163,7 163,7 @@ begin  -- architecture a1
       ci_multiframe_clk   => '0',
       ci_reset            => reset,
       ci_request_sync     => '0',
-      di_transceiver_data => di_transceiver_data,
+      di_data => di_data,
       co_nsynced          => co_nsynced,
       co_error            => co_error,
       do_samples          => do_samples,


@@ 177,7 177,7 @@ begin  -- architecture a1
         ena     => '1',
         KI      => di_lane_data(i).k,
         datain  => di_lane_data(i).data,
-        dataout => di_transceiver_data(i));
+        dataout => di_data(i));
   end generate encoders;
 
   char_clk <= not char_clk after char_clk_period/2;

@@ 126,7 126,7 @@ architecture a1 of jesd204b_rx_ils_tb is
   constant char_clk_period : time := 1 ns;    -- The clock period
   constant frame_clk_period : time := 1 ns * F;    -- The clock period
 
-  signal di_transceiver_data : lane_input_array(L-1 downto 0);
+  signal di_data : lane_input_array(L-1 downto 0);
   signal di_lane_data : lane_data_array(L-1 downto 0);
 
   signal char_clk : std_logic := '0';        -- The clock


@@ 159,7 159,7 @@ begin  -- architecture a1
       ci_multiframe_clk   => '0',
       ci_reset            => reset,
       ci_request_sync     => '0',
-      di_transceiver_data => di_transceiver_data,
+      di_data => di_data,
       co_nsynced          => co_nsynced,
       co_error            => co_error,
       do_samples          => do_samples,


@@ 173,7 173,7 @@ begin  -- architecture a1
         ena     => '1',
         KI      => di_lane_data(i).k,
         datain  => di_lane_data(i).data,
-        dataout => di_transceiver_data(i));
+        dataout => di_data(i));
   end generate encoders;
 
   char_clk <= not char_clk after char_clk_period/2;

@@ 67,7 67,7 @@ architecture a1 of jesd204b_rx_kchars_tb is
   constant char_clk_period : time := 1 ns;    -- The clock period
   constant frame_clk_period : time := 1 ns * F;    -- The clock period
 
-  signal di_transceiver_data : lane_input_array(L-1 downto 0);
+  signal di_data : lane_input_array(L-1 downto 0);
 
   signal char_clk : std_logic := '0';        -- The clock
   signal frame_clk : std_logic := '0';        -- The clock


@@ 99,7 99,7 @@ begin  -- architecture a1
       ci_multiframe_clk   => '0',
       ci_reset            => reset,
       ci_request_sync     => '0',
-      di_transceiver_data => di_transceiver_data,
+      di_data => di_data,
       co_nsynced          => co_nsynced,
       co_error            => co_error,
       do_samples          => do_samples,


@@ 117,11 117,11 @@ begin  -- architecture a1
       test_vec_index <= i;
       if i = 0 then
         for c in 0 to L-1 loop
-          di_transceiver_data(c) <= char_prepend & test_vectors(0).data(c)(9 downto char_offset);
+          di_data(c) <= char_prepend & test_vectors(0).data(c)(9 downto char_offset);
         end loop;  -- l
       else
         for c in 0 to L-1 loop
-          di_transceiver_data(c) <= test_vectors(i-1).data(c)(char_offset - 1 downto 0) & test_vectors(i).data(c)(9 downto char_offset);
+          di_data(c) <= test_vectors(i-1).data(c)(char_offset - 1 downto 0) & test_vectors(i).data(c)(9 downto char_offset);
         end loop;  -- l
       end if;
       wait for char_clk_period;