@@ 0,0 1,35 @@
+From ed3fed8d76a424cea002c5569769e46895c72139 Mon Sep 17 00:00:00 2001
+From: Vagrant Cascadian <vagrant@debian.org>
+Date: Thu, 3 Jul 2025 23:00:06 +0000
+Subject: [PATCH 2/3] Revert "phy: rockchip: samsung-hdptx: Fix clock ratio
+ setup"
+
+This reverts commit e3f71127c6d9b33bd714a957fd62c72abd87c182.
+---
+ drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+index 5547f8df8e71..56d8f25c1852 100644
+--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+@@ -192,7 +192,6 @@
+ #define LN3_TX_SER_RATE_SEL_HBR2	BIT(3)
+ #define LN3_TX_SER_RATE_SEL_HBR3	BIT(2)
+ 
+-#define HDMI14_MAX_RATE			340000000
+ #define HDMI20_MAX_RATE			600000000
+ 
+ struct lcpll_config {
+@@ -854,7 +853,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
+ 
+ 	regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
+ 
+-	if (rate > HDMI14_MAX_RATE / 100) {
++	if (rate >= 3400000) {
+ 		/* For 1/40 bitrate clk */
+ 		rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
+ 	} else {
+-- 
+2.50.0
+


@@ 0,0 1,42 @@
+From 678346ae18cd6b705993001826fd1d9e2e69e73b Mon Sep 17 00:00:00 2001
+From: Vagrant Cascadian <vagrant@debian.org>
+Date: Thu, 3 Jul 2025 23:00:26 +0000
+Subject: [PATCH 3/3] Revert "phy: rockchip: samsung-hdptx: Do no set
+ rk_hdptx_phy->rate in case of errors"
+
+This reverts commit 5aac41632fffe7eb4708d9e88e203a2cb13283c9.
+---
+ drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+index 56d8f25c1852..9b99fdd43f5f 100644
+--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+@@ -780,7 +780,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
+ {
+ 	const struct ropll_config *cfg = NULL;
+ 	struct ropll_config rc = {0};
+-	int ret, i;
++	int i;
++
++	hdptx->rate = rate * 100;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
+ 		if (rate == ropll_tmds_cfg[i].bit_rate) {
+@@ -839,11 +841,7 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
+ 	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
+ 			   PLL_PCG_CLK_EN);
+ 
+-	ret = rk_hdptx_post_enable_pll(hdptx);
+-	if (!ret)
+-		hdptx->rate = rate * 100;
+-
+-	return ret;
++	return rk_hdptx_post_enable_pll(hdptx);
+ }
+ 
+ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
+-- 
+2.50.0
+


@@ 0,0 1,94 @@
+From 3119142ea31ec13a64fbb6246f40ca9315b49b21 Mon Sep 17 00:00:00 2001
+From: Vagrant Cascadian <vagrant@debian.org>
+Date: Sun, 15 Jun 2025 02:19:50 +0000
+Subject: [PATCH 1/3] Revert "drm/rockchip: vop2: Improve display modes
+ handling on RK3588 HDMI0"
+
+This reverts commit d2b58a10228a906d46155eb7c15d79f39be25b37.
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 34 --------------------
+ 1 file changed, 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+index 5d7df4c3b08c..2aab2a095678 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -157,7 +157,6 @@ struct vop2_video_port {
+ 	struct drm_crtc crtc;
+ 	struct vop2 *vop2;
+ 	struct clk *dclk;
+-	struct clk *dclk_src;
+ 	unsigned int id;
+ 	const struct vop2_video_port_data *data;
+ 
+@@ -212,7 +211,6 @@ struct vop2 {
+ 	struct clk *hclk;
+ 	struct clk *aclk;
+ 	struct clk *pclk;
+-	struct clk *pll_hdmiphy0;
+ 
+ 	/* optional internal rgb encoder */
+ 	struct rockchip_rgb *rgb;
+@@ -221,8 +219,6 @@ struct vop2 {
+ 	struct vop2_win win[];
+ };
+ 
+-#define VOP2_MAX_DCLK_RATE		600000000
+-
+ #define vop2_output_if_is_hdmi(x)	((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
+ 					 (x) == ROCKCHIP_VOP2_EP_HDMI1)
+ 
+@@ -1055,9 +1051,6 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
+ 
+ 	vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
+ 
+-	if (vp->dclk_src)
+-		clk_set_parent(vp->dclk, vp->dclk_src);
+-
+ 	clk_disable_unprepare(vp->dclk);
+ 
+ 	vop2->enable_count--;
+@@ -2078,27 +2071,6 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
+ 
+-	/*
+-	 * Switch to HDMI PHY PLL as DCLK source for display modes up
+-	 * to 4K@60Hz, if available, otherwise keep using the system CRU.
+-	 */
+-	if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) {
+-		drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
+-			struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+-
+-			if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) {
+-				if (!vp->dclk_src)
+-					vp->dclk_src = clk_get_parent(vp->dclk);
+-
+-				ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0);
+-				if (ret < 0)
+-					drm_warn(vop2->drm,
+-						 "Could not switch to HDMI0 PHY PLL: %d\n", ret);
+-				break;
+-			}
+-		}
+-	}
+-
+ 	clk_set_rate(vp->dclk, clock);
+ 
+ 	vop2_post_config(crtc);
+@@ -3270,12 +3242,6 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
+ 		return PTR_ERR(vop2->pclk);
+ 	}
+ 
+-	vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0");
+-	if (IS_ERR(vop2->pll_hdmiphy0)) {
+-		drm_err(vop2->drm, "failed to get pll_hdmiphy0\n");
+-		return PTR_ERR(vop2->pll_hdmiphy0);
+-	}
+-
+ 	vop2->irq = platform_get_irq(pdev, 0);
+ 	if (vop2->irq < 0) {
+ 		drm_err(vop2->drm, "cannot find irq for vop2\n");
+-- 
+2.50.0
+