~ruther/guix-local

3d55f5c6b96fb237e7114422bffc4de0c8182e24 — Cayetano Santos 8 months ago 3282a00
gnu: verilator: Improve style.

* gnu/packages/fpga.scm (verilator)[arguments]: Use G-Expressions.

Change-Id: I3c04b4a632baaa8f2ff2f79354954fccafbbfd4a
Signed-off-by: Ludovic Courtès <ludo@gnu.org>
1 files changed, 22 insertions(+), 20 deletions(-)

M gnu/packages/fpga.scm
M gnu/packages/fpga.scm => gnu/packages/fpga.scm +22 -20
@@ 795,29 795,31 @@ using different abstraction levels.")
     (list perl python systemc))
    (build-system gnu-build-system)
    (arguments
     '(#:phases
       (modify-phases %standard-phases
         (replace 'bootstrap
           (lambda _ (invoke "autoconf")))
         (add-after 'unpack 'adjust-source
           (lambda _
             (substitute* "bin/verilator"
               (("/bin/echo") "echo"))))
         (add-before 'check 'disable-gdb-safe-path
           (lambda _
             (setenv "HOME" (getcwd))
             (mkdir-p (string-append (getcwd) "/.config/gdb"))
             (with-output-to-file (string-append (getcwd) "/.config/gdb/gdbinit")
               (lambda ()
                 (display "set auto-load safe-path /"))))))
       #:test-target "test"))
     (list
      #:phases
      #~(modify-phases %standard-phases
          (replace 'bootstrap
            (lambda _ (invoke "autoconf")))
          (add-after 'unpack 'adjust-source
            (lambda _
              (substitute* "bin/verilator"
                (("/bin/echo") "echo"))))
          (add-before 'check 'disable-gdb-safe-path
            (lambda _
              (setenv "HOME" (getcwd))
              (mkdir-p (string-append (getcwd) "/.config/gdb"))
              (with-output-to-file
                  (string-append (getcwd) "/.config/gdb/gdbinit")
                (lambda ()
                  (display "set auto-load safe-path /"))))))
      #:test-target "test"))
    (home-page "https://www.veripool.org/verilator/")
    (synopsis "Verilog/SystemVerilog simulator")
    (description
     "Verilator transforms the specified Verilog or SystemVerilog code by reading it,
performing lint checks, and optionally inserting assertion checks and
coverage-analysis points.  It outputs single- or multi-threaded @file{.cpp}
and @file{.h} files.")
     "Verilator transforms the specified Verilog or SystemVerilog code by
reading it, performing lint checks, and optionally inserting assertion checks
and coverage-analysis points.  It outputs single- or multi-threaded
@file{.cpp} and @file{.h} files.")
    (license license:lgpl3)))

(define-public fftgen