~ruther/guix-local

116e0e8644757d18eb54dc598934cba003ab8218 — Efraim Flashner 11 months ago 6df0405 
gnu: libgcrypt: Fix building on armhf-linux.

* gnu/packages/gnupg.scm (libgcrypt)[arguments]: When building for
armhf-linux add a phase applying a patch.
* gnu/packages/patches/libgcrypt-arm32-register-pressure.patch: New file.
* gnu/local.mk (dist_patch_DATA): Register it.

Change-Id: I858cfe69bac20bde2d88113c80634fb5f413e6dc
patch browse .tar.gz .zip 
3 files changed, 147 insertions(+), 1 deletions(-)

M gnu/local.mk
M gnu/packages/gnupg.scm
A gnu/packages/patches/libgcrypt-arm32-register-pressure.patch

M gnu/local.mk => gnu/local.mk +1 -0
@@ 1749,6 1749,7 @@ dist_patch_DATA =						\
  %D%/packages/patches/libcroco-CVE-2020-12825.patch		\
  %D%/packages/patches/libcyaml-libyaml-compat.patch		\
  %D%/packages/patches/libexpected-use-provided-catch2.patch	\
  %D%/packages/patches/libgcrypt-arm32-register-pressure.patch	\
  %D%/packages/patches/libgda-CVE-2021-39359.patch		\
  %D%/packages/patches/libgda-disable-data-proxy-test.patch     \
  %D%/packages/patches/libgda-fix-build.patch			\


M gnu/packages/gnupg.scm => gnu/packages/gnupg.scm +13 -1
@@ 4,7 4,7 @@
;;; Copyright © 2014, 2018 Eric Bavier <bavier@member.fsf.org>
;;; Copyright © 2014, 2015, 2016, 2020 Mark H Weaver <mhw@netris.org>
;;; Copyright © 2015 Paul van der Walt <paul@denknerd.org>
;;; Copyright © 2015-2021, 2024 Efraim Flashner <efraim@flashner.co.il>
;;; Copyright © 2015-2021, 2024, 2025 Efraim Flashner <efraim@flashner.co.il>
;;; Copyright © 2015, 2016, 2017, 2019, 2025 Ricardo Wurmus <rekado@elephly.net>
;;; Copyright © 2016 Christine Lemmer-Webber <cwebber@dustycloud.org>
;;; Copyright © 2016, 2017 Nikita <nikita@n0.is>


@@ 207,6 207,18 @@ Daemon and possibly more in the future.")
                  (add-before 'configure 'setenv
                    (lambda _
                      (setenv "GCRYPT_NO_BENCHMARKS" "t")))))
             '())
       ,@(if (target-arm32?)
             (list
               #:phases
               #~(modify-phases %standard-phases
                   (add-after 'unpack 'apply-upstream-patch
                     (lambda _
                       (let ((patch-file
                               #$(local-file
                                   (search-patch
                                     "libgcrypt-arm32-register-pressure.patch"))))
                         (invoke "patch" "--force" "-p1" "-i" patch-file))))))
             '())))
    (outputs '("out" "debug"))
    (home-page "https://gnupg.org/")


A gnu/packages/patches/libgcrypt-arm32-register-pressure.patch => gnu/packages/patches/libgcrypt-arm32-register-pressure.patch +133 -0
@@ 0,0 1,133 @@
This patch is from upstream and probably can be dropped with any version
after 1.11.0.

From 9c93b4607adcf9b3efd53aba43e2d33bf5aef9df Mon Sep 17 00:00:00 2001
From: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Date: Sun, 4 Aug 2024 18:04:49 +0300
Subject: [PATCH] mpi/ec-inline: reduce register pressure on 32-bit ARM

* mpi/ec-inline.h [HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS] (ADD4_LIMB32)
(ADD6_LIMB32, SUB4_LIMB32, SUB6_LIMB32): Reuse input registers
as output (use just two unique operators).
--

This fixes building ec-nist.c with GCC-14 on 32-bit ARM.

GnuPG-bug-id: 7226
Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
---
 mpi/ec-inline.h | 63 ++++++++++++++++++++++++-------------------------
 1 file changed, 31 insertions(+), 32 deletions(-)

diff --git a/mpi/ec-inline.h b/mpi/ec-inline.h
index c24d5352..3a526246 100644
--- a/mpi/ec-inline.h
+++ b/mpi/ec-inline.h
@@ -836,18 +836,18 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
 #ifdef HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS
 
 #define ADD4_LIMB32(A3, A2, A1, A0, B3, B2, B1, B0, C3, C2, C1, C0) \
-  __asm__ ("adds %3, %7, %11\n" \
-	   "adcs %2, %6, %10\n" \
-	   "adcs %1, %5, %9\n" \
-	   "adc  %0, %4, %8\n" \
+  __asm__ ("adds %3, %3, %11\n" \
+	   "adcs %2, %2, %10\n" \
+	   "adcs %1, %1, %9\n" \
+	   "adc  %0, %0, %8\n" \
 	   : "=r" (A3), \
 	     "=&r" (A2), \
 	     "=&r" (A1), \
 	     "=&r" (A0) \
-	   : "r" ((mpi_limb_t)(B3)), \
-	     "r" ((mpi_limb_t)(B2)), \
-	     "r" ((mpi_limb_t)(B1)), \
-	     "r" ((mpi_limb_t)(B0)), \
+	   : "0" ((mpi_limb_t)(B3)), \
+	     "1" ((mpi_limb_t)(B2)), \
+	     "2" ((mpi_limb_t)(B1)), \
+	     "3" ((mpi_limb_t)(B0)), \
 	     "Ir" ((mpi_limb_t)(C3)), \
 	     "Ir" ((mpi_limb_t)(C2)), \
 	     "Ir" ((mpi_limb_t)(C1)), \
@@ -857,18 +857,18 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
 #define ADD6_LIMB32(A5, A4, A3, A2, A1, A0, B5, B4, B3, B2, B1, B0, \
 		    C5, C4, C3, C2, C1, C0) do { \
     mpi_limb_t __carry6_32; \
-    __asm__ ("adds %3, %7, %10\n" \
-	     "adcs %2, %6, %9\n" \
-	     "adcs %1, %5, %8\n" \
-	     "adc  %0, %4, %4\n" \
+    __asm__ ("adds %3, %3, %10\n" \
+	     "adcs %2, %2, %9\n" \
+	     "adcs %1, %1, %8\n" \
+	     "adc  %0, %0, %0\n" \
 	     : "=r" (__carry6_32), \
 	       "=&r" (A2), \
 	       "=&r" (A1), \
 	       "=&r" (A0) \
-	     : "r" ((mpi_limb_t)(0)), \
-	       "r" ((mpi_limb_t)(B2)), \
-	       "r" ((mpi_limb_t)(B1)), \
-	       "r" ((mpi_limb_t)(B0)), \
+	     : "0" ((mpi_limb_t)(0)), \
+	       "1" ((mpi_limb_t)(B2)), \
+	       "2" ((mpi_limb_t)(B1)), \
+	       "3" ((mpi_limb_t)(B0)), \
 	       "Ir" ((mpi_limb_t)(C2)), \
 	       "Ir" ((mpi_limb_t)(C1)), \
 	       "Ir" ((mpi_limb_t)(C0)) \
@@ -878,18 +878,18 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
   } while (0)
 
 #define SUB4_LIMB32(A3, A2, A1, A0, B3, B2, B1, B0, C3, C2, C1, C0) \
-  __asm__ ("subs %3, %7, %11\n" \
-	   "sbcs %2, %6, %10\n" \
-	   "sbcs %1, %5, %9\n" \
-	   "sbc  %0, %4, %8\n" \
+  __asm__ ("subs %3, %3, %11\n" \
+	   "sbcs %2, %2, %10\n" \
+	   "sbcs %1, %1, %9\n" \
+	   "sbc  %0, %0, %8\n" \
 	   : "=r" (A3), \
 	     "=&r" (A2), \
 	     "=&r" (A1), \
 	     "=&r" (A0) \
-	   : "r" ((mpi_limb_t)(B3)), \
-	     "r" ((mpi_limb_t)(B2)), \
-	     "r" ((mpi_limb_t)(B1)), \
-	     "r" ((mpi_limb_t)(B0)), \
+	   : "0" ((mpi_limb_t)(B3)), \
+	     "1" ((mpi_limb_t)(B2)), \
+	     "2" ((mpi_limb_t)(B1)), \
+	     "3" ((mpi_limb_t)(B0)), \
 	     "Ir" ((mpi_limb_t)(C3)), \
 	     "Ir" ((mpi_limb_t)(C2)), \
 	     "Ir" ((mpi_limb_t)(C1)), \
@@ -899,18 +899,17 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
 #define SUB6_LIMB32(A5, A4, A3, A2, A1, A0, B5, B4, B3, B2, B1, B0, \
 		    C5, C4, C3, C2, C1, C0) do { \
     mpi_limb_t __borrow6_32; \
-    __asm__ ("subs %3, %7, %10\n" \
-	     "sbcs %2, %6, %9\n" \
-	     "sbcs %1, %5, %8\n" \
-	     "sbc  %0, %4, %4\n" \
+    __asm__ ("subs %3, %3, %9\n" \
+	     "sbcs %2, %2, %8\n" \
+	     "sbcs %1, %1, %7\n" \
+	     "sbc  %0, %0, %0\n" \
 	     : "=r" (__borrow6_32), \
 	       "=&r" (A2), \
 	       "=&r" (A1), \
 	       "=&r" (A0) \
-	     : "r" ((mpi_limb_t)(0)), \
-	       "r" ((mpi_limb_t)(B2)), \
-	       "r" ((mpi_limb_t)(B1)), \
-	       "r" ((mpi_limb_t)(B0)), \
+	     : "1" ((mpi_limb_t)(B2)), \
+	       "2" ((mpi_limb_t)(B1)), \
+	       "3" ((mpi_limb_t)(B0)), \
 	       "Ir" ((mpi_limb_t)(C2)), \
 	       "Ir" ((mpi_limb_t)(C1)), \
 	       "Ir" ((mpi_limb_t)(C0)) \
--