From 34353779a473764722895bc413e1522606254b4e Mon Sep 17 00:00:00 2001 From: Rutherther Date: Mon, 12 May 2025 14:51:44 +0200 Subject: [PATCH] Initial commit --- .../zynqmp/packages/boards/kr260/pm_cfg_obj.c | 495 ++++++++++++++++++ modules/zynqmp/packages/bootloader.scm | 109 ++++ modules/zynqmp/packages/firmware.scm | 82 +++ modules/zynqmp/packages/microblaze.scm | 141 +++++ ...kbuild-fdtoverlay-changes-from-linux.patch | 198 +++++++ ...s-and-add-new-dtb-entries-for-zynqmp.patch | 91 ++++ ...for-pointing-to-separate-description.patch | 66 +++ ...64-zynqmp-describe-empty-binman-node.patch | 64 +++ ...ynqmp-add-binman-description-for-som.patch | 345 ++++++++++++ ...u-boot.itb-and-qspi-image-via-binman.patch | 159 ++++++ 10 files changed, 1750 insertions(+) create mode 100644 modules/zynqmp/packages/boards/kr260/pm_cfg_obj.c create mode 100644 modules/zynqmp/packages/bootloader.scm create mode 100644 modules/zynqmp/packages/firmware.scm create mode 100644 modules/zynqmp/packages/microblaze.scm create mode 100644 modules/zynqmp/packages/patches/uboot/0001-kbuild-cherry-pick-kbuild-fdtoverlay-changes-from-linux.patch create mode 100644 modules/zynqmp/packages/patches/uboot/0002-arm64-zynqmp-remove-overlays-and-add-new-dtb-entries-for-zynqmp.patch create mode 100644 modules/zynqmp/packages/patches/uboot/0003-binman-add-option-for-pointing-to-separate-description.patch create mode 100644 modules/zynqmp/packages/patches/uboot/0004-arm64-zynqmp-describe-empty-binman-node.patch create mode 100644 modules/zynqmp/packages/patches/uboot/0005-arm64-zynqmp-add-binman-description-for-som.patch create mode 100644 modules/zynqmp/packages/patches/uboot/0006-arm64-zynqmp-generate-u-boot.itb-and-qspi-image-via-binman.patch diff --git a/modules/zynqmp/packages/boards/kr260/pm_cfg_obj.c b/modules/zynqmp/packages/boards/kr260/pm_cfg_obj.c new file mode 100644 index 0000000000000000000000000000000000000000..17ac97ac9daf6084291d307d95f108bfeb3b2370 --- /dev/null +++ b/modules/zynqmp/packages/boards/kr260/pm_cfg_obj.c @@ -0,0 +1,495 @@ +/****************************************************************************** +* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include "xil_types.h" +#include "pm_defs.h" + +#define PM_CONFIG_MASTER_SECTION_ID 0x101U +#define PM_CONFIG_SLAVE_SECTION_ID 0x102U +#define PM_CONFIG_PREALLOC_SECTION_ID 0x103U +#define PM_CONFIG_POWER_SECTION_ID 0x104U +#define PM_CONFIG_RESET_SECTION_ID 0x105U +#define PM_CONFIG_SHUTDOWN_SECTION_ID 0x106U +#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U +#define PM_CONFIG_GPO_SECTION_ID 0x108U + +#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U +#define PM_MASTER_USING_SLAVE_MASK 0x2U + +#define PM_CONFIG_GPO1_MIO_PIN_34_MAP (1U << 10U) +#define PM_CONFIG_GPO1_MIO_PIN_35_MAP (1U << 11U) +#define PM_CONFIG_GPO1_MIO_PIN_36_MAP (1U << 12U) +#define PM_CONFIG_GPO1_MIO_PIN_37_MAP (1U << 13U) + +#define PM_CONFIG_GPO1_BIT_2_MASK (1U << 2U) +#define PM_CONFIG_GPO1_BIT_3_MASK (1U << 3U) +#define PM_CONFIG_GPO1_BIT_4_MASK (1U << 4U) +#define PM_CONFIG_GPO1_BIT_5_MASK (1U << 5U) + +#define SUSPEND_TIMEOUT 0xFFFFFFFFU + +#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U + + +#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001 +#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100 +#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200 + + + +#if defined (__ICCARM__) +#pragma language=save +#pragma language=extended +#endif +#if defined (__GNUC__) + const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) = +#elif defined (__ICCARM__) +#pragma location = ".sys_cfg_data" +__root const u32 XPm_ConfigObject[] = +#endif +{ + /**********************************************************************/ + /* HEADER */ + 2, /* Number of remaining words in the header */ + 8, /* Number of sections included in config object */ + PM_CONFIG_OBJECT_TYPE_BASE, /* Type of config object as base */ + /**********************************************************************/ + /* MASTER SECTION */ + PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */ + 3U, /* No. of Masters*/ + + NODE_APU, /* Master Node ID */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask of this master */ + SUSPEND_TIMEOUT, /* Suspend timeout */ + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */ + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */ + + NODE_RPU_0, /* Master Node ID */ + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask of this master */ + SUSPEND_TIMEOUT, /* Suspend timeout */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */ + + NODE_RPU_1, /* Master Node ID */ + PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask of this master */ + SUSPEND_TIMEOUT, /* Suspend timeout */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Suspend permissions */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Wake permissions */ + + + /**********************************************************************/ + /* SLAVE SECTION */ + + + PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */ + 35, /* Number of slaves */ + + NODE_OCM_BANK_0, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_OCM_BANK_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_OCM_BANK_2, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_OCM_BANK_3, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_TCM_0_A, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */ + + NODE_TCM_0_B, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */ + + NODE_TCM_1_A, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_TCM_1_B, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_L2, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_GPU_PP_0, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_GPU_PP_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_USB_0, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_USB_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_TTC_0, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_TTC_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_TTC_2, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_TTC_3, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_ETH_0, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_ETH_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_UART_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_SPI_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_I2C_1, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_DP, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_GDMA, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_ADMA, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_QSPI, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_GPIO, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_EXTERN, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_DDR, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_IPI_APU, + 0U, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask */ + + NODE_IPI_RPU_0, + 0U, + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */ + + NODE_IPI_RPU_1, + 0U, + PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_GPU, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_RTC, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + NODE_PL, + PM_SLAVE_FLAG_IS_SHAREABLE, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + + + /**********************************************************************/ + /* PREALLOC SECTION */ + + PM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */ + 3U, /* No. of Masters*/ + +/* Prealloc for psu_cortexa53_0 */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, + 10, + NODE_DDR, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_L2, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_OCM_BANK_0, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_OCM_BANK_1, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_OCM_BANK_2, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_OCM_BANK_3, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_I2C_1, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_QSPI, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_PL, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_IPI_APU, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + + /* Prealloc for psu_cortexr5_0 */ + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, + 3, + NODE_TCM_0_A, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_TCM_0_B, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_IPI_RPU_0, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + + /* Prealloc for psu_cortexr5_1 */ + PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + 3, + NODE_TCM_1_A, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_TCM_1_B, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + NODE_IPI_RPU_1, + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + + + + /**********************************************************************/ + /* POWER SECTION */ + + PM_CONFIG_POWER_SECTION_ID, /* Power Section ID */ + 4U, /* Number of power nodes */ + + NODE_APU, /* Power node ID */ + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */ + + NODE_RPU, /* Power node ID */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */ + + NODE_FPD, /* Power node ID */ + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */ + + NODE_PLD, /* Power node ID */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */ + + + /**********************************************************************/ + /* RESET SECTION */ + + PM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */ + 120U, /* Number of resets */ + + XILPM_RESET_PCIE_CFG, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_PCIE_BRIDGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_PCIE_CTRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_DP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SWDT_CRF, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_AFI_FM5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_AFI_FM4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_AFI_FM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_AFI_FM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_AFI_FM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_AFI_FM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GDMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPU_PP1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPU_PP0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPU, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SATA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU3_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU2_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU1_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU0_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_APU_L2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ACPU0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_DDR, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_APM_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SOFT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GEM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GEM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GEM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GEM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_QSPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_UART0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_UART1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SPI0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SPI1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SDIO0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SDIO1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_CAN0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_CAN1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_I2C0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_I2C1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_TTC0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_TTC1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_TTC2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_TTC3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SWDT_CRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_NAND, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_ADMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPIO, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_IOU_CC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_TIMESTAMP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RPU_R50, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RPU_R51, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RPU_AMBA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_OCM, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RPU_PGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_USB0_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_USB1_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_USB0_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_USB1_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_USB0_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_USB1_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_IPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_APM_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RTC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_SYSMON, 0, + XILPM_RESET_AFI_FM6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_LPD_SWDT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_FPD, PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, + XILPM_RESET_RPU_DBG1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RPU_DBG0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_DBG_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_DBG_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_APLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_DPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_VPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_IOPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_7, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_8, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_9, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_10, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_11, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_12, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_13, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_14, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_15, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_16, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_17, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_18, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_19, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_20, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_21, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_22, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_23, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_24, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_25, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_26, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_27, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_28, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_29, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_30, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPO3_PL_31, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_RPU_LS, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_PS_ONLY, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_PL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPIO5_EMIO_92, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPIO5_EMIO_93, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPIO5_EMIO_94, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + XILPM_RESET_GPIO5_EMIO_95, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, + + /**********************************************************************/ + /* SET CONFIG SECTION */ + PM_CONFIG_SET_CONFIG_SECTION_ID, /* Set Config Section ID */ + 0U, /* Permissions to load base config object */ + 0U, /* Permissions to load overlay config object */ + + /**********************************************************************/ + /* SHUTDOWN SECTION */ + + PM_CONFIG_SHUTDOWN_SECTION_ID, /* Shutdown Section ID */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* System Shutdown/Restart Permission */ + + /**********************************************************************/ + /* GPO SECTION */ + PM_CONFIG_GPO_SECTION_ID, /* GPO Section ID */ + PM_CONFIG_GPO1_MIO_PIN_35_MAP | + 0, /* State of GPO pins */ +}; +#if defined (__ICCARM__) +#pragma language=restore +#endif diff --git a/modules/zynqmp/packages/bootloader.scm b/modules/zynqmp/packages/bootloader.scm new file mode 100644 index 0000000000000000000000000000000000000000..782a7aced8f9ef27e8c0ff0306f738cefef4692b --- /dev/null +++ b/modules/zynqmp/packages/bootloader.scm @@ -0,0 +1,109 @@ +(define-module (zynqmp packages bootloader) + #:use-module (zynqmp packages firmware) + #:use-module ((guix licenses) #:prefix license:) + #:use-module (guix packages) + #:use-module (guix download) + #:use-module (guix gexp) + #:use-module (guix utils) + #:use-module (guix git-download) + #:use-module (guix build-system gnu) + #:use-module (gnu packages) + #:use-module (gnu packages tls) + #:use-module (gnu packages bootloaders) + #:use-module (gnu packages texinfo) + #:use-module (gnu packages cross-base) + #:use-module (gnu packages base) + #:use-module (gnu packages bash) + #:use-module (gnu packages firmware) + #:export (u-boot-for-kr260)) + +(define (search-patch patch) + (parameterize ((%patch-path (map + (lambda (directory) + (string-append directory "/zynqmp/packages/patches")) + %load-path))) + ((@ (gnu packages) search-patch) patch))) + +(define-syntax-rule (search-patches file-name ...) + "Return the list of absolute file names corresponding to each +FILE-NAME found in %PATCH-PATH." + (list (search-patch file-name) ...)) + +;; (define* (u-boot-for-kria #:configs configs)) + +(define u-boot-for-kr260 + (let ((base (make-u-boot-package + "xilinx_zynqmp_kria" + "aarch64-linux-gnu" + #:configs + '("CONFIG_SPL_FS_FAT=y" + "CONFIG_SPL_MMC=y" + "CONFIG_SPL_FS_LOAD_PAYLOAD_NAME=\"u-boot.itb\"" + "CONFIG_PMUFW_INIT_FILE=\"./tmp/pmufw.bin\"" + "CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE=\"./tmp/pm_cfg_obj.bin\""))) + ;; TODO ... + (pmcfg-obj-c (local-file "modules/zynqmp/packages/boards/kr260/pm_cfg_obj.c"))) + (package + (inherit base) + (name "u-boot-for-kr260") + (version "2024.01_2024.2") + (source + (origin + ;; (inherit (package-source base)) + (method git-fetch) + (uri (git-reference + (url "https://github.com/Xilinx/u-boot-xlnx") + (commit "xlnx_rebase_v2024.01_2024.2"))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1gqcriiy9zglff0f88j6pin230yc10jfysylpga0v0pgj1pazv59")) + (patches + (append + (search-patches + "uboot/0001-kbuild-cherry-pick-kbuild-fdtoverlay-changes-from-linux.patch" + "uboot/0002-arm64-zynqmp-remove-overlays-and-add-new-dtb-entries-for-zynqmp.patch" + "uboot/0003-binman-add-option-for-pointing-to-separate-description.patch" + "uboot/0004-arm64-zynqmp-describe-empty-binman-node.patch" + "uboot/0005-arm64-zynqmp-add-binman-description-for-som.patch" + "uboot/0006-arm64-zynqmp-generate-u-boot.itb-and-qspi-image-via-binman.patch") + (origin-patches (package-source base)))))) + (native-inputs + (modify-inputs (package-native-inputs base) + (append openssl))) + (inputs + (modify-inputs (package-inputs base) + (append arm-trusted-firmware-for-zynqmp) + (append xilinx-zynqmp-pmufw))) + (arguments + (substitute-keyword-arguments (package-arguments base) + ((#:phases phases #f) + #~(modify-phases #$phases + (delete 'disable-tools-libcrypto) + (add-before 'build 'pmufw-setup + (lambda* (#:key native-inputs inputs #:allow-other-keys) + (mkdir-p "tmp") + (let ((pmufw-elf (search-input-file inputs "pmufw.elf")) + (target "tmp/pmufw.bin")) + (invoke "objcopy" + "-O" "binary" + "-I" "elf32-little" + pmufw-elf + target)) + (let ((pmufw-cfg #$pmcfg-obj-c) + (target "tmp/pm_cfg_obj.bin")) + (invoke + (string-append (getcwd) "/tools/zynqmp_pm_cfg_obj_convert.py") + pmufw-cfg + target)))) + ;; Good for booting via JTAG + (add-after 'install 'install-uboot-spl-elf + (lambda _ + (install-file "spl/u-boot-spl" + (string-append #$output "/libexec/spl")))) + (add-after 'unpack 'set-environment + (lambda* (#:key native-inputs inputs #:allow-other-keys) + (setenv "BL31" (search-input-file inputs "bl31.bin")))))) + ((#:make-flags flags '()) + #~(cons* + "DEVICE_TREE=zynqmp-sm-k26-revA" + #$flags))))))) diff --git a/modules/zynqmp/packages/firmware.scm b/modules/zynqmp/packages/firmware.scm new file mode 100644 index 0000000000000000000000000000000000000000..c840f1a248f5d22fddc983d2312cb20a3adbf1a6 --- /dev/null +++ b/modules/zynqmp/packages/firmware.scm @@ -0,0 +1,82 @@ +(define-module (zynqmp packages firmware) + #:use-module (zynqmp packages microblaze) + #:use-module ((guix licenses) #:prefix license:) + #:use-module (guix packages) + #:use-module (guix download) + #:use-module (guix gexp) + #:use-module (guix utils) + #:use-module (guix git-download) + #:use-module (guix build-system gnu) + #:use-module (gnu packages) + #:use-module (gnu packages tls) + #:use-module (gnu packages bootloaders) + #:use-module (gnu packages texinfo) + #:use-module (gnu packages cross-base) + #:use-module (gnu packages base) + #:use-module (gnu packages bash) + #:use-module (gnu packages firmware) + + #:export (arm-trusted-firmware-for-zynqmp + xilinx-zynqmp-pmufw)) + +(define arm-trusted-firmware-for-zynqmp + (let* ((base ((@@ (gnu packages firmware )make-arm-trusted-firmware) + "zynqmp" + #:make-flags '("ZYNQMP_CONSOLE=cadence1") + #:triplet "aarch64-linux-gnu"))) + (package + (inherit base) + (name "xilinx-arm-trusted-firmware") + (version "2.10_2024.2") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/Xilinx/arm-trusted-firmware") + (commit "xlnx_rebase_v2.10_2024.2"))) + (file-name (git-file-name name version)) + (sha256 + (base32 "0li43y96y696dgprsp3dvdv2n6kslcbmswfjp42cmyjwfrml7bvf"))))))) + +(define xilinx-embeddedsw-source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/Xilinx/embeddedsw") + (commit "xilinx_v2024.2"))) + (sha256 + (base32 "0zlnbcpxp00pf09mz7n0958d558fy1q4a3ipljcm2k1qfkaihv4g")) )) + +(define xilinx-zynqmp-pmufw + (package + (name "xilinx-zynqmp-pmufw") + (version "2024.2") + (source xilinx-embeddedsw-source) + (build-system gnu-build-system) + (arguments + (list + #:target "microblazeel-xilinx-elf" + #:make-flags #~(list + "CFLAGS=-Os -flto -ffat-lto-objects -DK26_SOM" + (string-append "COMPILER=" #$(cc-for-target "microblazeel-xilinx-elf")) + (string-append "ARCHIVER=" #$(cc-for-target "microblazeel-xilinx-elf") "-ar") + (string-append "CC=" #$(cc-for-target "microblazeel-xilinx-elf"))) + #:phases #~(modify-phases %standard-phases + (delete 'configure) + (add-before 'build 'cd + (lambda _ + (chdir "lib/sw_apps/zynqmp_pmufw/src"))) + (replace 'install + (lambda _ + (mkdir-p #$output) + (copy-file + "executable.elf" + (string-append #$output "/pmufw.elf"))))))) + (native-inputs + (list + microblazeel-xilinx-elf-toolchain + bash)) + (description "") + (synopsis "") + (license license:expat) + (home-page "https://github.com/Xilinx/embeddedsw"))) diff --git a/modules/zynqmp/packages/microblaze.scm b/modules/zynqmp/packages/microblaze.scm new file mode 100644 index 0000000000000000000000000000000000000000..8874e4145f0b9c8c48fdaef2f6d2e3b54e5d8ff1 --- /dev/null +++ b/modules/zynqmp/packages/microblaze.scm @@ -0,0 +1,141 @@ +(define-module (zynqmp packages microblaze) + #:use-module (zynqmp packages microblaze) + #:use-module ((guix licenses) #:prefix license:) + #:use-module (guix packages) + #:use-module (guix memoization) + #:use-module (guix download) + #:use-module (guix build utils) + #:use-module (guix gexp) + #:use-module (guix utils) + #:use-module (guix git-download) + #:use-module (guix build-system gnu) + #:use-module (guix build-system trivial) + #:use-module (gnu packages) + #:use-module (gnu packages tls) + #:use-module (gnu packages bootloaders) + #:use-module (gnu packages texinfo) + #:use-module (gnu packages cross-base) + #:use-module (gnu packages base) + #:use-module (gnu packages bash) + #:use-module (gnu packages firmware) + #:export (binutils-2.43 + + microblazeel-xilinx-elf-gcc + microblazeel-xilinx-elf-newlib + microblazeel-xilinx-elf-toolchain)) + +(define binutils-2.43 + (package + (inherit binutils) + (name "binutils") + (version "2.43") + (source + (origin + (method url-fetch) + (uri (string-append "mirror://gnu/binutils/binutils-" + version ".tar.bz2")) + (sha256 + (base32 "0l77cprf7d7zff5ygrdlrcy5jxrjqnw81c27mahs9xqdgw3w7lzy")) + (patches (search-patches "binutils-loongson-workaround.patch")))))) + +(define microblazeel-xilinx-elf-newlib + (let* ((target "microblazeel-xilinx-elf") + (xgcc (cross-gcc target)) + (xbinutils (cross-binutils target #:binutils binutils-2.43))) + (package + (name "newlib") + (version "4.5.0.20241231") + (native-search-paths + (list (search-path-specification + (variable "CROSS_C_INCLUDE_PATH") + (files '("microblazeel-xilinx-elf/include"))) + (search-path-specification + (variable "CROSS_LIBRARY_PATH") + (files '("microblazeel-xilinx-elf/lib"))))) + (source (origin + (method url-fetch) + (uri (string-append "ftp://sourceware.org/pub/newlib/newlib-" + version ".tar.gz")) + (sha256 + (base32 + "0ln8r0p0yqy0p1diy04r2zwhlfs67qmkih95djcnaj85w02jdw9k")))) + (build-system gnu-build-system) + (arguments + (list + ;; The configure flags are identical to the flags used by the "GCC ARM + ;; embedded" project. + #:configure-flags #~(list + #$(string-append "--target=" target) + "--enable-newlib-io-long-long" + "--enable-newlib-register-fini" + "--disable-newlib-supplied-syscalls" + "--disable-nls") + #:make-flags ''("MAKE_INFO=TRUE") + #:phases + #~(modify-phases %standard-phases + (add-after 'unpack 'fix-references-to-/bin/sh + (lambda _ + (substitute* (find-files "libgloss" "^Makefile\\.in$") + (("/bin/sh") (which "sh"))) + #t))))) + (native-inputs + `(("xbinutils" ,xbinutils) + ("xgcc" ,xgcc) + ("texinfo" ,texinfo))) + (home-page "https://www.sourceware.org/newlib/") + (synopsis "C library for use on embedded systems") + (description "Newlib is a C library intended for use on embedded +systems. It is a conglomeration of several library parts that are easily +usable on embedded products.") + (license (license:non-copyleft + "https://www.sourceware.org/newlib/COPYING.NEWLIB"))))) + +(define make-microblaze-toolchain + (mlambda (xgcc newlib) + "Produce a cross-compiler toolchain package with the compiler XGCC and the +C library variant NEWLIB." + (let* ((nano? (string=? (package-name newlib) + "newlib-nano")) + (newlib-with-xgcc + (package + (inherit newlib) + (native-inputs + (alist-replace "xgcc" (list xgcc) + (package-native-inputs newlib)))))) + (package + (name "miroblazeel-xilinx-elf-toolchain") + (version (package-version xgcc)) + (source #f) + (build-system trivial-build-system) + (arguments + '(#:modules ((guix build union)) + #:builder + (begin + (use-modules (ice-9 match) + (guix build union)) + (match %build-inputs + (((names . directories) ...) + (union-build (assoc-ref %outputs "out") + directories)))))) + (propagated-inputs + `(("binutils" ,microblazeel-xilinx-elf-binutils) + ("gcc" ,xgcc) + ("newlib" ,newlib-with-xgcc))) + (synopsis "Complete GCC tool chain for Microblaze bare metal development") + (description "This package provides a complete GCC tool chain for Microblaze +bare metal development. This includes the GCC microblazeel-xilinx-elf cross compiler +and newlib as the C library. The supported programming +languages are C and C++.") + (home-page (package-home-page xgcc)) + (license (package-license xgcc)))))) + +(define microblazeel-xilinx-elf-binutils + (cross-binutils "microblazeel-xilinx-elf" #:binutils binutils-2.43)) + +(define microblazeel-xilinx-elf-gcc + (cross-gcc "microblazeel-xilinx-elf" + #:xbinutils microblazeel-xilinx-elf-binutils)) + +(define microblazeel-xilinx-elf-toolchain + (make-microblaze-toolchain microblazeel-xilinx-elf-gcc + microblazeel-xilinx-elf-newlib)) diff --git a/modules/zynqmp/packages/patches/uboot/0001-kbuild-cherry-pick-kbuild-fdtoverlay-changes-from-linux.patch b/modules/zynqmp/packages/patches/uboot/0001-kbuild-cherry-pick-kbuild-fdtoverlay-changes-from-linux.patch new file mode 100644 index 0000000000000000000000000000000000000000..cf7f101af413cccaaac4598407a84fd55b007b88 --- /dev/null +++ b/modules/zynqmp/packages/patches/uboot/0001-kbuild-cherry-pick-kbuild-fdtoverlay-changes-from-linux.patch @@ -0,0 +1,198 @@ +From: Prasad Kummari +Date: Fri, 6 Sep 2024 12:38:07 +0530 +Subject: [PATCH] kbuild: cherry-pick kbuild fdtoverlay changes from linux + +Linux commits: +15d16d6dadf6 kbuild: Add generic rule to apply fdtoverlay +44f87191d105 kbuild: parameterize the .o part of suffix-search + +The Linux commit 15d16d6dadf6 adds a generic rule in Makefile.lib +to automatically apply fdtoverlay, so that each platform doesn't +need to include a complex rule. This also automatically appends +DTC_FLAGS_foo_base += -@ to all base files + +The platform's Makefile only needs to have this now: + +foo-dtbs := foo_base.dtb foo_overlay1.dtbo foo_overlay2.dtbo +dtb-y := foo.dtb + +Signed-off-by: Prasad Kummari +Reviewed-by: Tom Rini +Signed-off-by: Michal Simek +Link: https://lore.kernel.org/r/20240906070808.1045991-2-prasad.kummari@amd.com +Upstream: https://source.denx.de/u-boot/u-boot/-/commit/10de9b5a6a5b53a37600894115685f00d3bbfc2d +--- + arch/arm/dts/Makefile | 57 ++++++++++++++++++++++++++++++++++++++++++ + scripts/Kbuild.include | 4 +++ + scripts/Makefile.build | 1 + + scripts/Makefile.lib | 27 ++++++++++++++++++++ + 4 files changed, 89 insertions(+) + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 48ca62521b8..8b6f65a61a2 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -477,6 +477,63 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ + zynqmp-zc1751-xm017-dc3.dtb \ + zynqmp-zc1751-xm018-dc4.dtb \ + zynqmp-zc1751-xm019-dc5.dtb ++ ++zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo ++zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo ++zynqmp-p-a2197-00-revA-x-prc-03-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo ++zynqmp-p-a2197-00-revA-x-prc-04-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo ++zynqmp-p-a2197-00-revA-x-prc-05-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo ++ ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-01-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb ++ ++zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo ++zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo ++zynqmp-sc-vhk158-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vhk158-revA.dtbo ++zynqmp-sc-vpk120-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk120-revB.dtbo ++zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo ++zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo ++zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo ++ ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vhk158-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk120-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb ++ ++zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo ++zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo ++zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo ++zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo ++ ++zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo ++zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo ++zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo ++zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo ++ ++zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo ++zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo ++zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo ++zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo ++ ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb ++ + dtb-$(CONFIG_ARCH_VERSAL) += \ + versal-emb-plus-ve2302-revA.dtb \ + versal-mini.dtb \ +diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include +index 62e0207f91b..5daceb26061 100644 +--- a/scripts/Kbuild.include ++++ b/scripts/Kbuild.include +@@ -31,6 +31,10 @@ baseprereq = $(basename $(notdir $<)) + # Escape single quote for use in echo statements + escsq = $(subst $(squote),'\$(squote)',$1) + ++### ++# real prerequisites without phony targets ++real-prereqs = $(filter-out $(PHONY), $^) ++ + ### + # Easy method for doing a status message + kecho := : +diff --git a/scripts/Makefile.build b/scripts/Makefile.build +index 97dd4a64f6e..b3bb8e558d3 100644 +--- a/scripts/Makefile.build ++++ b/scripts/Makefile.build +@@ -293,6 +293,7 @@ $(obj)/%.o: $(src)/%.S FORCE + + targets += $(real-objs-y) $(real-objs-m) $(lib-y) + targets += $(extra-y) $(MAKECMDGOALS) $(always) ++targets += $(real-dtb-y) $(lib-y) $(always-y) + + # Linker scripts preprocessor (.lds.S -> .lds) + # --------------------------------------------------------------------------- +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 16bbc277a9f..b867941816d 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -47,6 +47,13 @@ obj-m := $(filter-out %/, $(obj-m)) + + subdir-ym := $(sort $(subdir-y) $(subdir-m)) + ++# Expand $(foo-objs) $(foo-y) etc. by replacing their individuals ++suffix-search = $(strip $(foreach s, $3, $($(1:%$(strip $2)=%$s)))) ++# List composite targets that are constructed by combining other targets ++multi-search = $(sort $(foreach m, $1, $(if $(call suffix-search, $m, $2, $3 -), $m))) ++# List primitive targets that are compiled from source files ++real-search = $(foreach m, $1, $(if $(call suffix-search, $m, $2, $3 -), $(call suffix-search, $m, $2, $3), $m)) ++ + # if $(foo-objs) exists, foo.o is a composite object + multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m)))) + multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m)))) +@@ -58,6 +65,13 @@ single-used-m := $(sort $(filter-out $(multi-used-m),$(obj-m))) + multi-objs-y := $(foreach m, $(multi-used-y), $($(m:.o=-objs)) $($(m:.o=-y))) + multi-objs-m := $(foreach m, $(multi-used-m), $($(m:.o=-objs)) $($(m:.o=-y))) + ++# Composite DTB (i.e. DTB constructed by overlay) ++multi-dtb-y := $(call multi-search, $(dtb-y), .dtb, -dtbs) ++# Primitive DTB compiled from *.dts ++real-dtb-y := $(call real-search, $(dtb-y), .dtb, -dtbs) ++# Base DTB that overlay is applied onto (each first word of $(*-dtbs) expansion) ++base-dtb-y := $(foreach m, $(multi-dtb-y), $(firstword $(call suffix-search, $m, .dtb, -dtbs))) ++ + # $(subdir-obj-y) is the list of objects in $(obj-y) which uses dir/ to + # tell kbuild to descend + subdir-obj-y := $(filter %/built-in.o, $(obj-y)) +@@ -69,6 +83,7 @@ real-objs-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y) + # Add subdir path + + extra-y := $(addprefix $(obj)/,$(extra-y)) ++always-y := $(addprefix $(obj)/,$(always-y)) + always := $(addprefix $(obj)/,$(always)) + targets := $(addprefix $(obj)/,$(targets)) + modorder := $(addprefix $(obj)/,$(modorder)) +@@ -83,6 +98,8 @@ multi-used-y := $(addprefix $(obj)/,$(multi-used-y)) + multi-used-m := $(addprefix $(obj)/,$(multi-used-m)) + multi-objs-y := $(addprefix $(obj)/,$(multi-objs-y)) + multi-objs-m := $(addprefix $(obj)/,$(multi-objs-m)) ++multi-dtb-y := $(addprefix $(obj)/,$(multi-dtb-y)) ++real-dtb-y := $(addprefix $(obj)/,$(real-dtb-y)) + subdir-ym := $(addprefix $(obj)/,$(subdir-ym)) + + # These flags are needed for modversions and compiling, so we define them here +@@ -296,6 +313,9 @@ endif + + DTC_FLAGS += $(DTC_FLAGS_$(basetarget)) + ++# Set -@ if the target is a base DTB that overlay is applied onto ++DTC_FLAGS += $(if $(filter $(patsubst $(obj)/%,%,$@), $(base-dtb-y)), -@) ++ + # Generate an assembly file to wrap the output of the device tree compiler + quiet_cmd_dt_S_dtb= DTB $@ + # Modified for U-Boot +@@ -382,6 +402,13 @@ $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtco) + ++quiet_cmd_fdtoverlay = DTOVL $@ ++ cmd_fdtoverlay = fdtoverlay -o $@ -i $(real-prereqs) ++ ++$(multi-dtb-y): FORCE ++ $(call if_changed,fdtoverlay) ++$(call multi_depend, $(multi-dtb-y), .dtb, -dtbs) ++ + # Fonts + # --------------------------------------------------------------------------- + diff --git a/modules/zynqmp/packages/patches/uboot/0002-arm64-zynqmp-remove-overlays-and-add-new-dtb-entries-for-zynqmp.patch b/modules/zynqmp/packages/patches/uboot/0002-arm64-zynqmp-remove-overlays-and-add-new-dtb-entries-for-zynqmp.patch new file mode 100644 index 0000000000000000000000000000000000000000..975200137fdf63c07a70dae5d697def28ee35fe1 --- /dev/null +++ b/modules/zynqmp/packages/patches/uboot/0002-arm64-zynqmp-remove-overlays-and-add-new-dtb-entries-for-zynqmp.patch @@ -0,0 +1,91 @@ +From: Prasad Kummari +Date: Fri, 6 Sep 2024 12:38:08 +0530 +Subject: [PATCH] arm64: zynqmp: Remove overlays and add new dtb entries for + ZynqMP + +Remove device tree overlay (DTBO) entries for the ZynqMP target +from the Makefile. Add new device tree binaries (DTBs) for the +zynqmp-sm-k24-revA and zynqmp-smk-k24-revA configurations. + +Signed-off-by: Prasad Kummari +Signed-off-by: Michal Simek +Link: https://lore.kernel.org/r/20240906070808.1045991-3-prasad.kummari@amd.com +Upstream: https://source.denx.de/u-boot/u-boot/-/commit/290385f374fba69f9c4f473c8bd25d64935a4c82 +--- + arch/arm/dts/Makefile | 24 ++++++------------------ + 1 file changed, 6 insertions(+), 18 deletions(-) + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 8b6f65a61a2..35623380673 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -414,11 +414,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ + zynqmp-m-a2197-02-revA.dtb \ + zynqmp-m-a2197-03-revA.dtb \ + zynqmp-p-a2197-00-revA.dtb \ +- zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \ +- zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \ +- zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \ +- zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \ +- zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \ + zynqmp-mini.dtb \ + zynqmp-mini-emmc0.dtb \ + zynqmp-mini-emmc1.dtb \ +@@ -433,23 +428,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ + zynqmp-mini-qspi-x2-stacked.dtb \ + zynqmp-sc-revB.dtb \ + zynqmp-sc-revC.dtb \ +- zynqmp-sc-vek280-revA.dtbo \ +- zynqmp-sc-vek280-revB.dtbo \ +- zynqmp-sc-vhk158-revA.dtbo \ +- zynqmp-sc-vpk120-revB.dtbo \ +- zynqmp-sc-vpk180-revA.dtbo \ +- zynqmp-sc-vpk180-revB.dtbo \ +- zynqmp-sc-vn-p-b2197-00-revA.dtbo \ +- zynqmp-sc-vm-p-m1369-00-revA.dtbo \ + zynqmp-sm-k24-revA.dtb \ + zynqmp-smk-k24-revA.dtb \ + zynqmp-sm-k26-revA.dtb \ + zynqmp-smk-k26-revA.dtb \ +- zynqmp-sck-kd-g-revA.dtbo \ +- zynqmp-sck-kr-g-revA.dtbo \ +- zynqmp-sck-kr-g-revB.dtbo \ +- zynqmp-sck-kv-g-revA.dtbo \ +- zynqmp-sck-kv-g-revB.dtbo \ + zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ + zynqmp-vpk120-revA.dtb \ + zynqmp-vp-x-a2785-00-revA.dtb \ +@@ -497,6 +479,7 @@ zynqmp-sc-vpk120-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk120-revB.dtbo + zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo + zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo + zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo ++zynqmp-sc-vm-p-b1369-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vm-p-m1369-00-revA.dtbo + + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb +@@ -505,6 +488,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk120-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vm-p-b1369-00-revA.dtb + + zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo + zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +@@ -520,6 +504,8 @@ zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g- + zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo + zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo + zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo ++zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo ++zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo + + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb +@@ -533,6 +519,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb + + dtb-$(CONFIG_ARCH_VERSAL) += \ + versal-emb-plus-ve2302-revA.dtb \ diff --git a/modules/zynqmp/packages/patches/uboot/0003-binman-add-option-for-pointing-to-separate-description.patch b/modules/zynqmp/packages/patches/uboot/0003-binman-add-option-for-pointing-to-separate-description.patch new file mode 100644 index 0000000000000000000000000000000000000000..76343afcc3611a7137c5c49f9e96f506efd5527a --- /dev/null +++ b/modules/zynqmp/packages/patches/uboot/0003-binman-add-option-for-pointing-to-separate-description.patch @@ -0,0 +1,66 @@ +From: Michal Simek +Date: Fri, 1 Nov 2024 10:17:54 +0100 +Subject: [PATCH] binman: Add option for pointing to separate description + +Adding binman node with target images description can be unwanted feature +but as of today there is no way to disable it. +Also on size constrained systems it is not useful to add binman description +to DTB. +Introduce BINMAN_DTB Kconfig symbol which allows separate DTB for target +from DTB for binman itself. + +Signed-off-by: Michal Simek +Link: https://lore.kernel.org/r/f1379d2587f9bf279a7a75c318aabbc1b35ee0c6.1730452668.git.michal.simek@amd.com +Upstream: https://source.denx.de/u-boot/u-boot/-/commit/d92fdb60677b3990919a4216d3452418db215224 +--- + Makefile | 11 ++++++++++- + lib/Kconfig | 9 +++++++++ + 2 files changed, 19 insertions(+), 1 deletion(-) + +diff --git a/Makefile b/Makefile +index f049d77dcaf..cb0ff66eccf 100644 +--- a/Makefile ++++ b/Makefile +@@ -1337,12 +1337,21 @@ u-boot.ldr: u-boot + # Use 'make BINMAN_VERBOSE=3' to set vebosity level + default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE)) + ++binman_dtb := $(shell echo $(CONFIG_BINMAN_DTB)) ++ifeq ($(strip $(binman_dtb)),) ++ifeq ($(CONFIG_OF_EMBED),y) ++binman_dtb = ./dts/dt.dtb ++else ++binman_dtb = ./u-boot.dtb ++endif ++endif ++ + quiet_cmd_binman = BINMAN $@ + cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ + $(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \ + --toolpath $(objtree)/tools \ + $(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \ +- build -u -d u-boot.dtb -O . -m \ ++ build -u -d $(binman_dtb) -O . -m \ + --allow-missing $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \ + -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ + -I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \ +diff --git a/lib/Kconfig b/lib/Kconfig +index d47df6bb1cf..a1ee51e6eae 100644 +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -45,6 +45,15 @@ config BINMAN_FDT + locate entries in the firmware image. See binman.h for the available + functionality. + ++config BINMAN_DTB ++ string "binman DTB description" ++ depends on BINMAN ++ help ++ This enables option to point to different DTB file with binman node which ++ is outside of DTB used by the firmware. Use this option if information ++ about generated images shouldn't be the part of target binary. Or on system ++ with limited storage. ++ + config CC_OPTIMIZE_LIBS_FOR_SPEED + bool "Optimize libraries for speed" + help diff --git a/modules/zynqmp/packages/patches/uboot/0004-arm64-zynqmp-describe-empty-binman-node.patch b/modules/zynqmp/packages/patches/uboot/0004-arm64-zynqmp-describe-empty-binman-node.patch new file mode 100644 index 0000000000000000000000000000000000000000..b2923f619962047d9baffbe92d3c333f51524397 --- /dev/null +++ b/modules/zynqmp/packages/patches/uboot/0004-arm64-zynqmp-describe-empty-binman-node.patch @@ -0,0 +1,64 @@ +From: Michal Simek +Date: Fri, 1 Nov 2024 10:17:56 +0100 +Subject: [PATCH] arm64: zynqmp: Describe empty binman node + +For enabling binman by default there is a need to have at least empty node +present that's why create -u-boot.dtsi with empty node to cover all ZynqMP +platforms. + +Signed-off-by: Michal Simek +Link: https://lore.kernel.org/r/14d874ad4568fa8e3178e893224fecc5c676f04c.1730452668.git.michal.simek@amd.com +Upstream: https://source.denx.de/u-boot/u-boot/-/commit/afbc1fa5f18a2eebf1cf06f62574016edc093f50 +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/zynqmp-binman-mini.dts | 10 ++++++++++ + arch/arm/dts/zynqmp-u-boot.dtsi | 11 +++++++++++ + 3 files changed, 22 insertions(+) + create mode 100644 arch/arm/dts/zynqmp-binman-mini.dts + create mode 100644 arch/arm/dts/zynqmp-u-boot.dtsi + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 35623380673..4bdfb204ae3 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -426,6 +426,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ + zynqmp-mini-qspi-x1-stacked.dtb \ + zynqmp-mini-qspi-x2-single.dtb \ + zynqmp-mini-qspi-x2-stacked.dtb \ ++ zynqmp-binman-mini.dtb \ + zynqmp-sc-revB.dtb \ + zynqmp-sc-revC.dtb \ + zynqmp-sm-k24-revA.dtb \ +diff --git a/arch/arm/dts/zynqmp-binman-mini.dts b/arch/arm/dts/zynqmp-binman-mini.dts +new file mode 100644 +index 00000000000..8f3d18ef394 +--- /dev/null ++++ b/arch/arm/dts/zynqmp-binman-mini.dts +@@ -0,0 +1,10 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * (C) Copyright 2024, Advanced Micro Devices, Inc. ++ * ++ * Michal Simek ++ */ ++ ++/dts-v1/; ++ ++#include "zynqmp-u-boot.dtsi" +diff --git a/arch/arm/dts/zynqmp-u-boot.dtsi b/arch/arm/dts/zynqmp-u-boot.dtsi +new file mode 100644 +index 00000000000..9a7527ed5a1 +--- /dev/null ++++ b/arch/arm/dts/zynqmp-u-boot.dtsi +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * (C) Copyright 2024, Advanced Micro Devices, Inc. ++ * ++ * Michal Simek ++ */ ++ ++/ { ++ binman: binman { ++ }; ++}; diff --git a/modules/zynqmp/packages/patches/uboot/0005-arm64-zynqmp-add-binman-description-for-som.patch b/modules/zynqmp/packages/patches/uboot/0005-arm64-zynqmp-add-binman-description-for-som.patch new file mode 100644 index 0000000000000000000000000000000000000000..82b5ba8bc020fb213fd456c9c3a6f5c2d74da1dc --- /dev/null +++ b/modules/zynqmp/packages/patches/uboot/0005-arm64-zynqmp-add-binman-description-for-som.patch @@ -0,0 +1,345 @@ +From: Michal Simek +Date: Fri, 1 Nov 2024 10:17:57 +0100 +Subject: [PATCH] arm64: zynqmp: Add binman description for SOM + +There is necessary to do some steps to compose boot images. These steps +were in scripts in layers for a while. That's why introduce description via +binman to simplify wiring and remove all scripting around. +This should make sure that everybody is up2date with the latest versions. + +The first step is to create fit image with DTBs with descriptions in +configuration node which is written as regular expression to match all SOM +versions. +Description is there for k24 and k26 in spite of low level psu_init +configuration is different. The reason is that it goes to u-boot.itb image +which is the same for k24 and k26. +u-boot.itb is another image which is generated. It is normally generated +via arch/arm/mach-zynqmp/mkimage_fit_atf.sh but this script is supposed to +be deprecated. +FIT image by purpose is using 64bit addresses to have default option to +move images to high DDR (above 4GB). TF-A and TEE are optional components +but in the most cases TF-A is present all the time and TEE(OP-TEE) is used +by some configurations too. + +3rd generated image is boot.bin with updated user field which contains +version number. This image can be used with updated Image Selector +which supports A/B update mechanisms with rollback protection. + +4th image is image.bin which binary file which contains boot.bin and +u-boot.itb together and can be programmed via origin Image Selector. +This image can be also used for creating one capsule which contains both +boot images (in SPL boot flow). + +Signed-off-by: Michal Simek +Link: https://lore.kernel.org/r/35bc47a4a4799c5f5dbea56a45340a2810538330.1730452668.git.michal.simek@amd.com +Upstream: https://source.denx.de/u-boot/u-boot/-/commit/2eb8cd5bd4936a5eb2e77729855d946f6720921c +--- + arch/arm/Kconfig | 1 + + arch/arm/dts/Makefile | 1 + + arch/arm/dts/zynqmp-binman-som.dts | 225 +++++++++++++++++++++++++++ + arch/arm/mach-zynqmp/Kconfig | 14 ++ + configs/xilinx_zynqmp_kria_defconfig | 3 + + 5 files changed, 244 insertions(+) + create mode 100644 arch/arm/dts/zynqmp-binman-som.dts + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index cbe72103aab..dca493eaf55 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1302,6 +1302,7 @@ config ARCH_ZYNQMP_R5 + config ARCH_ZYNQMP + bool "Xilinx ZynqMP based platform" + select ARM64 ++ select BINMAN + select CLK + select DM + select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 4bdfb204ae3..4653b5bdd16 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -522,6 +522,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman-som.dtb + + dtb-$(CONFIG_ARCH_VERSAL) += \ + versal-emb-plus-ve2302-revA.dtb \ +diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts +new file mode 100644 +index 00000000000..3d9d8476c98 +--- /dev/null ++++ b/arch/arm/dts/zynqmp-binman-som.dts +@@ -0,0 +1,225 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * dts file for Xilinx ZynqMP SOMs (k24/k26) ++ * ++ * (C) Copyright 2024, Advanced Micro Devices, Inc. ++ * ++ * Michal Simek ++ */ ++ ++#include ++ ++/dts-v1/; ++/ { ++ binman: binman { ++ multiple-images; ++ fit-dtb.blob { ++ filename = "fit-dtb.blob"; ++ pad-byte = <0>; ++ fit { ++ fit,align = <0x8>; ++ fit,external-offset = <0x0>; ++ description = "DTBs for SOMs+CCs"; ++ fit,fdt-list-val = "zynqmp-smk-k26-revA", "zynqmp-smk-k26-revA-sck-kr-g-revA", ++ "zynqmp-smk-k26-revA-sck-kr-g-revB", "zynqmp-smk-k26-revA-sck-kv-g-revA", ++ "zynqmp-smk-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kv-g-revA", ++ "zynqmp-sm-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kr-g-revB", ++ "zynqmp-smk-k24-revA-sck-kd-g-revA", "zynqmp-smk-k24-revA-sck-kv-g-revB", ++ "zynqmp-smk-k24-revA-sck-kr-g-revB", "zynqmp-sm-k24-revA-sck-kd-g-revA", ++ "zynqmp-sm-k24-revA-sck-kv-g-revB", "zynqmp-sm-k24-revA-sck-kr-g-revB"; ++ ++ images { ++ @fdt-SEQ { ++ description = "NAME"; ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ hash-1 { ++ algo = "md5"; ++ }; ++ }; ++ }; ++ configurations { ++ default = "conf-1"; ++ conf-1 { ++ description = "SOM itself"; ++ fdt = "fdt-1"; ++ }; ++ conf-2 { ++ description = "zynqmp-smk-k26-.*-sck-kr-g-revA"; ++ fdt = "fdt-2"; ++ }; ++ conf-3 { ++ description = "zynqmp-smk-k26-.*-sck-kr-g-.*"; ++ fdt = "fdt-3"; ++ }; ++ conf-4 { ++ description = "zynqmp-smk-k26-.*-sck-kv-g-rev[AZ]"; ++ fdt = "fdt-4"; ++ }; ++ conf-5 { ++ description = "zynqmp-smk-k26-.*-sck-kv-g-.*"; ++ fdt = "fdt-5"; ++ }; ++ conf-6 { ++ description = "zynqmp-sm-k26-.*-sck-kv-g-rev[AZ]"; ++ fdt = "fdt-6"; ++ }; ++ conf-7 { ++ description = "zynqmp-sm-k26-.*-sck-kv-g-.*"; ++ fdt = "fdt-7"; ++ }; ++ conf-8 { ++ description = "zynqmp-sm-k26-.*-sck-kr-g-.*"; ++ fdt = "fdt-8"; ++ }; ++ conf-9 { ++ description = "zynqmp-smk-k24-.*-sck-kd-g-.*"; ++ fdt = "fdt-9"; ++ }; ++ conf-10 { ++ description = "zynqmp-smk-k24-.*-sck-kv-g-.*"; ++ fdt = "fdt-10"; ++ }; ++ conf-11 { ++ description = "zynqmp-smk-k24-.*-sck-kr-g-.*"; ++ fdt = "fdt-11"; ++ }; ++ conf-12 { ++ description = "zynqmp-sm-k24-.*-sck-kd-g-.*"; ++ fdt = "fdt-12"; ++ }; ++ conf-13 { ++ description = "zynqmp-sm-k24-.*-sck-kv-g-.*"; ++ fdt = "fdt-13"; ++ }; ++ conf-14 { ++ description = "zynqmp-sm-k24-.*-sck-kr-g-.*"; ++ fdt = "fdt-14"; ++ }; ++ }; ++ }; ++ }; ++ ++ /* u-boot.itb generation in a static way */ ++ itb { ++ filename = "u-boot.itb"; ++ pad-byte = <0>; ++ ++ fit { ++ description = "Configuration for Xilinx ZynqMP SoC"; ++ fit,align = <0x8>; ++ fit,external-offset = <0x0>; ++ images { ++ uboot { ++ description = "U-Boot (64-bit)"; ++ type = "firmware"; ++ os = "u-boot"; ++ arch = "arm64"; ++ compression = "none"; ++ load = /bits/ 64 ; ++ entry = /bits/ 64 ; ++ hash { ++ algo = "md5"; ++ }; ++ u-boot-nodtb { ++ }; ++ }; ++ atf { ++ description = "Trusted Firmware-A"; ++ type = "firmware"; ++ os = "arm-trusted-firmware"; ++ arch = "arm64"; ++ compression = "none"; ++ load = /bits/ 64 ; ++ entry = /bits/ 64 ; ++ hash { ++ algo = "md5"; ++ }; ++ atf-bl31 { ++ optional; ++ }; ++ }; ++ tee { ++ description = "OP-TEE"; ++ type = "tee"; ++ arch = "arm64"; ++ compression = "none"; ++ os = "tee"; ++ load = /bits/ 64 ; ++ entry = /bits/ 64 ; ++ tee-os { ++ optional; ++ }; ++ }; ++ fdt { ++ description = "Multi DTB fit image"; ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ load = <0x0 0x100000>; ++ hash { ++ algo = "md5"; ++ }; ++ fdt-blob { ++ filename = "fit-dtb.blob"; ++ type = "blob-ext"; ++ }; ++ }; ++ }; ++ configurations { ++ default = "conf-1"; ++ conf-1 { ++ description = "Multi DTB with TF-A/TEE"; ++ firmware = "atf"; ++ loadables = "tee", "uboot", "fdt"; ++ }; ++ }; ++ }; ++ }; ++ ++ /* boot.bin generated with version string inside */ ++ bootimage { ++ filename = "boot.bin"; ++ pad-byte = <0>; ++ ++ blob-ext@1 { ++ offset = <0x0>; ++ filename = "spl/boot.bin"; ++ }; ++ /* Optional version string at offset 0x70 */ ++ blob-ext@2 { ++ offset = <0x70>; ++ filename = "version.bin"; ++ overlap; ++ optional; ++ }; ++ /* Optional version string at offset 0x94 */ ++ blob-ext@3 { ++ offset = <0x94>; ++ filename = "version.bin"; ++ overlap; ++ optional; ++ }; ++ }; ++ ++#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS ++ /* Full QSPI image for recovery app */ ++ image { ++ filename = "qspi.bin"; ++ pad-byte = <0>; ++ ++ blob-ext@1 { ++ offset = <0x0>; ++ filename = "boot.bin"; ++ }; ++ blob-ext@2 { ++ offset = ; ++ filename = "u-boot.itb"; ++ }; ++ fdtmap { ++ }; ++ }; ++#endif ++ }; ++}; +diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig +index 46c7fc75537..341c8379946 100644 +--- a/arch/arm/mach-zynqmp/Kconfig ++++ b/arch/arm/mach-zynqmp/Kconfig +@@ -140,6 +140,20 @@ config SPL_ZYNQMP_RESTORE_JTAG + even if no eFuses were burnt. This option restores the interface if + possible. + ++config BL31_LOAD_ADDR ++ hex "Load address of BL31 image (mostly TF-A)" ++ default 0xfffea000 ++ help ++ The load address for the BL31 image. This value is used to build the ++ FIT image header that places BL31 in memory where it will run. ++ ++config BL32_LOAD_ADDR ++ hex "Load address of BL32 image (mostly secure OS)" ++ default 0 ++ help ++ The load address for the BL32 image. This value is used to build the ++ FIT image header that places BL32 in memory where it will run. ++ + config ZYNQ_SDHCI_MAX_FREQ + default 200000000 + +diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig +index 32d40939ac1..7b0e1a63483 100644 +--- a/configs/xilinx_zynqmp_kria_defconfig ++++ b/configs/xilinx_zynqmp_kria_defconfig +@@ -39,6 +39,7 @@ CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_CLOCKS=y + CONFIG_SPL_MAX_SIZE=0x40000 + CONFIG_SPL_BSS_MAX_SIZE=0x80000 ++# CONFIG_SPL_BINMAN_SYMBOLS is not set + # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set + CONFIG_SPL_STACK_R=y + CONFIG_SPL_FS_LOAD_KERNEL_NAME="" +@@ -223,6 +224,8 @@ CONFIG_VIDEO_ZYNQMP_DPSUB=y + CONFIG_VIRTIO_MMIO=y + CONFIG_VIRTIO_NET=y + CONFIG_VIRTIO_BLK=y ++# CONFIG_BINMAN_FDT is not set ++CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-som.dtb" + CONFIG_PANIC_HANG=y + CONFIG_TPM=y + CONFIG_SPL_GZIP=y diff --git a/modules/zynqmp/packages/patches/uboot/0006-arm64-zynqmp-generate-u-boot.itb-and-qspi-image-via-binman.patch b/modules/zynqmp/packages/patches/uboot/0006-arm64-zynqmp-generate-u-boot.itb-and-qspi-image-via-binman.patch new file mode 100644 index 0000000000000000000000000000000000000000..af550139174969a9bacab68a72208505037e52b4 --- /dev/null +++ b/modules/zynqmp/packages/patches/uboot/0006-arm64-zynqmp-generate-u-boot.itb-and-qspi-image-via-binman.patch @@ -0,0 +1,159 @@ +From: Michal Simek +Date: Fri, 1 Nov 2024 10:17:58 +0100 +Subject: [PATCH] arm64: zynqmp: Generate u-boot.itb and QSPI image via binman + +u-boot.itb has been generated via mkimage_fit_atf.sh but it is on the way +out that's why convert it's description to binman. +Compare to script binman description is not able to configure BL31 and BL32 +load/entry addresses which should be done separately. + +Signed-off-by: Michal Simek +Link: https://lore.kernel.org/r/90b613796aee38158252c8bb1dfc3da0420f089d.1730452668.git.michal.simek@amd.com +Upstream: https://source.denx.de/u-boot/u-boot/-/commit/a4c98119109a60b9b236996f47065aa8fc0de9ca +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/zynqmp-binman.dts | 111 +++++++++++++++++++++++++++ + configs/xilinx_zynqmp_virt_defconfig | 3 + + 3 files changed, 115 insertions(+) + create mode 100644 arch/arm/dts/zynqmp-binman.dts + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 4653b5bdd16..f4e4149e85c 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -472,6 +472,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman.dtb + + zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo + zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo +diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts +new file mode 100644 +index 00000000000..df0fdf46510 +--- /dev/null ++++ b/arch/arm/dts/zynqmp-binman.dts +@@ -0,0 +1,111 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * dts file for Xilinx ZynqMP platforms ++ * ++ * (C) Copyright 2024, Advanced Micro Devices, Inc. ++ * ++ * Michal Simek ++ */ ++ ++#include ++ ++/dts-v1/; ++/ { ++ binman: binman { ++ multiple-images; ++ ++ /* u-boot.itb generation in a static way */ ++ itb { ++ filename = "u-boot.itb"; ++ pad-byte = <0>; ++ ++ fit { ++ description = "Configuration for Xilinx ZynqMP SoC"; ++ fit,align = <0x8>; ++ fit,external-offset = <0x0>; ++ fit,fdt-list = "of-list"; ++ images { ++ uboot { ++ description = "U-Boot (64-bit)"; ++ type = "firmware"; ++ os = "u-boot"; ++ arch = "arm64"; ++ compression = "none"; ++ load = /bits/ 64 ; ++ entry = /bits/ 64 ; ++ hash { ++ algo = "md5"; ++ }; ++ u-boot-nodtb { ++ }; ++ }; ++ atf { ++ description = "Trusted Firmware-A"; ++ type = "firmware"; ++ os = "arm-trusted-firmware"; ++ arch = "arm64"; ++ compression = "none"; ++ load = /bits/ 64 ; ++ entry = /bits/ 64 ; ++ hash { ++ algo = "md5"; ++ }; ++ atf-bl31 { ++ optional; ++ }; ++ }; ++ tee { ++ description = "OP-TEE"; ++ type = "tee"; ++ arch = "arm64"; ++ compression = "none"; ++ os = "tee"; ++ load = /bits/ 64 ; ++ entry = /bits/ 64 ; ++ tee-os { ++ optional; ++ }; ++ }; ++ @fdt-SEQ { ++ description = "NAME"; ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ load = <0x0 0x100000>; ++ hash-1 { ++ algo = "md5"; ++ }; ++ }; ++ }; ++ configurations { ++ default = "@conf-DEFAULT-SEQ"; ++ @conf-SEQ { ++ description = "NAME"; ++ firmware = "atf"; ++ loadables = "tee", "uboot"; ++ fdt = "fdt-SEQ"; ++ }; ++ }; ++ }; ++ }; ++ ++#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS ++ /* QSPI image for testing QSPI boot mode */ ++ image { ++ filename = "qspi.bin"; ++ pad-byte = <0>; ++ ++ blob-ext@1 { ++ offset = <0x0>; ++ filename = "spl/boot.bin"; ++ }; ++ blob-ext@2 { ++ offset = ; ++ filename = "u-boot.itb"; ++ }; ++ fdtmap { ++ }; ++ }; ++#endif ++ }; ++}; +diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig +index cc298b200a1..2643ce2acf7 100644 +--- a/configs/xilinx_zynqmp_virt_defconfig ++++ b/configs/xilinx_zynqmp_virt_defconfig +@@ -243,3 +243,6 @@ CONFIG_EFI_SET_TIME=y + CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y + CONFIG_EFI_CAPSULE_ON_DISK=y + CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y ++# CONFIG_SPL_BINMAN_SYMBOLS is not set ++# CONFIG_BINMAN_FDT is not set ++CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman.dtb"