From b48e753abdcd4fbe871295edd9a3314a03d92838 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Thu, 13 Jun 2024 20:11:14 +0200 Subject: [PATCH] feat: add vhdl treesitter mode --- init.el | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/init.el b/init.el index 9566ae4..833fc80 100644 --- a/init.el +++ b/init.el @@ -18,6 +18,7 @@ gcs-done)) (add-hook 'emacs-startup-hook #'efs/display-startup-time) + (my-use-package no-littering :ensure (:wait t) :demand t @@ -773,12 +774,14 @@ ;; VHDL (my-use-package vhdl-mode :ensure nil - :mode - ("\\.vhd\\'" . vhdl-mode) + ;; :mode + ;; vhdl-ts-mode instead + ;; ("\\.vhdl?\\'" . vhdl-mode) :hook ((vhdl-mode . lsp-deferred) ;; defer because of envrc (vhdl-mode . vhdl-electric-mode) - (vhdl-mode . vhdl-stutter-mode)) + (vhdl-mode . vhdl-stutter-mode) + (vhdl-mode . (lambda () (setq lsp-completion-enable nil)))) :custom (vhdl-clock-edge-condition 'function) (vhdl-clock-name "clk_i") @@ -787,6 +790,19 @@ (vhdl-basic-offset 2) (lsp-vhdl-server 'vhdl-ls)) +(my-use-package vhdl-ts-mode + :ensure t + :after vhdl-mode + :mode + ("\\.vhdl?\\'" . vhdl-ts-mode)) + +(my-use-package hydra + :ensure t) + +(my-use-package vhdl-ext + :ensure t + :after vhdl-mode) + ;; Verilog (my-use-package verilog-mode -- 2.48.1