From f72d85ee3b44f9bfb5faacbf26b0a04bbb50b579 Mon Sep 17 00:00:00 2001 From: Rahix Date: Sat, 11 May 2019 23:55:37 +0200 Subject: [PATCH] attiny85: Update USI patch Signed-off-by: Rahix --- patch/attiny85.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/patch/attiny85.yaml b/patch/attiny85.yaml index 010fb59..4cb99d1 100644 --- a/patch/attiny85.yaml +++ b/patch/attiny85.yaml @@ -3,9 +3,19 @@ _include: USI: USICR: + _modify: + USICLK: + access: write-only + USITC: + access: write-only USIWM: _replace_enum: - DISABLED: [0, "All detectors disabled. Port pins operates as normal."] - THREE_WIRE: [1, "Three-wire mode. Uses DO, DI, and USCK pins."] - TWO_WIRE_SLAVE: [2, "Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."] + DISABLED: [0, "All detectors disabled. Port pins operates as normal."] + THREE_WIRE: [1, "Three-wire mode. Uses DO, DI, and USCK pins."] + TWO_WIRE_SLAVE: [2, "Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."] TWO_WIRE_MASTER: [3, "Two-wire mode (Master). Uses SDA and SCL pins."] + USICS: + NO_CLOCK: [0, "No Clock/Software clock strobe"] + TC0: [1, "Timer/Counter0 Compare Match"] + EXT_POS: [2, "External, positive edge"] + EXT_NEG: [3, "External, negative edge"] -- 2.48.1