From f48ac82c4907373002d88562fa99c48b2a31a6c9 Mon Sep 17 00:00:00 2001 From: Andrew Dona-Couch Date: Mon, 17 Aug 2020 01:46:58 -0400 Subject: [PATCH] Add support for the ATtiny84 --- Cargo.toml | 1 + Makefile | 2 +- README.md | 1 + patch/attiny84.yaml | 220 +++++++++ patch/timer/attiny84.yaml | 14 + patch/timer/dev/16bit-tiny84-tc1.yaml | 30 ++ src/devices/mod.rs | 19 + src/lib.rs | 4 + vendor/attiny84.atdf | 685 ++++++++++++++++++++++++++ 9 files changed, 975 insertions(+), 1 deletion(-) create mode 100644 patch/attiny84.yaml create mode 100644 patch/timer/attiny84.yaml create mode 100644 patch/timer/dev/16bit-tiny84-tc1.yaml create mode 100644 vendor/attiny84.atdf diff --git a/Cargo.toml b/Cargo.toml index 76b455b..60fa8de 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -29,6 +29,7 @@ atmega328p = [] atmega48p = [] atmega32u4 = [] atmega64 = [] +attiny84 = [] attiny85 = [] attiny88 = [] rt = ["avr-device-macros"] diff --git a/Makefile b/Makefile index 2c48a7c..96fb6eb 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,6 @@ all: deps chips -CHIPS := atmega1280 atmega168 atmega2560 atmega8 atmega328p atmega32u4 atmega48p atmega64 attiny85 attiny88 +CHIPS := atmega1280 atmega168 atmega2560 atmega8 atmega328p atmega32u4 atmega48p atmega64 attiny84 attiny85 attiny88 RUSTUP_TOOLCHAIN ?= nightly diff --git a/README.md b/README.md index 4be3841..a9146a0 100644 --- a/README.md +++ b/README.md @@ -19,6 +19,7 @@ Via the feature you can select which chip you want the register specifications f * `atmega32u4` * `atmega48p` * `atmega64` +* `attiny84` * `attiny85` * `attiny88` diff --git a/patch/attiny84.yaml b/patch/attiny84.yaml new file mode 100644 index 0000000..33d97f1 --- /dev/null +++ b/patch/attiny84.yaml @@ -0,0 +1,220 @@ +_include: + - "common/ac.yaml" + - "common/wdt.yaml" + + - "timer/attiny84.yaml" + +AC: + _modify: + DIDR0: + description: "Digital Input Disable Register 0" + DIDR0: + _delete: + - ADC0D + _modify: + ADC1D: + description: "ADC1 (AIN0) Digital input buffer disable" + _add: + ADC2D: + description: "ADC2 (AIN1) Digital input buffer disable" + bitOffset: 2 + bitWidth: 1 + access: read-write +ADC: + ADCSRA: + ADPS: + _replace_enum: + PRESCALER_2: [1, "Prescaler Value 2"] + PRESCALER_4: [2, "Prescaler Value 4"] + PRESCALER_8: [3, "Prescaler Value 8"] + PRESCALER_16: [4, "Prescaler Value 16"] + PRESCALER_32: [5, "Prescaler Value 32"] + PRESCALER_64: [6, "Prescaler Value 64"] + PRESCALER_128: [7, "Prescaler Value 128"] + ADCSRB: + ADTS: + _replace_enum: + FREE: [0, "Free Running mode"] + AC: [1, "Analog Comparator"] + INT0: [2, "External Interrupt Request 0"] + TC0_CMA: [3, "Timer/Counter0 Compare Match A"] + TC0_OVF: [4, "Timer/Counter0 Overflow"] + TC0_CMB: [5, "Timer/Counter0 Compare Match B"] + PCIR: [6, "Pin Change Interrupt Request"] + ADMUX: + _add: + MUX: + description: "Analog Channel and Gain Selection Bits" + bitOffset: 0 + bitWidth: 6 + access: read-write + REFS: + description: "Reference Selection Bits" + bitOffset: 6 + bitWidth: 2 + access: read-write + MUX: + _write_constraint: enum + _replace_enum: + ADC0: [0, "Single-ended Input ADC0"] + ADC1: [1, "Single-ended Input ADC1"] + ADC2: [2, "Single-ended Input ADC2"] + ADC3: [3, "Single-ended Input ADC3"] + ADC4: [4, "Single-ended Input ADC4"] + ADC5: [5, "Single-ended Input ADC5"] + ADC6: [6, "Single-ended Input ADC6"] + ADC7: [7, "Single-ended Input ADC7"] + + ADC_GND: [32, "0V (GND)"] + ADC_VBG: [33, "Internal Reference (VBG)"] + TEMPSENS: [34, "Temperature sensor"] + + ADC0_ADC0_20X: [35, "Differential Inputs Positive ADC0 Negative ADC0 20x Gain"] + ADC0_ADC1_1X: [8, "Differential Inputs Positive ADC0 Negative ADC1 1x Gain"] + ADC0_ADC1_20X: [9, "Differential Inputs Postive ADC0 Negative ADC1 20x Gain"] + ADC0_ADC3_1X: [10, "Differential Inputs Positive ADC0 Negative ADC3 1x Gain"] + ADC0_ADC3_20X: [11, "Differential Inputs Positive ADC0 Negative ADC3 20x Gain"] + + ADC1_ADC0_1X: [40, "Differential Inputs Positive ADC1 Negative ADC0 1x Gain"] + ADC1_ADC0_20X: [41, "Differential Inputs Positive ADC1 Negative ADC0 20x Gain"] + ADC1_ADC2_1X: [12, "Differential Inputs Positive ADC1 Negative ADC2 1x Gain"] + ADC1_ADC2_20X: [13, "Differential Inputs Positive ADC1 Negative ADC2 20x Gain"] + ADC1_ADC3_1X: [14, "Differential Inputs Positive ADC1 Negative ADC3 1x Gain"] + ADC1_ADC3_20X: [15, "Differential Inputs Positive ADC1 Negative ADC3 20x Gain"] + + ADC2_ADC1_1X: [44, "Differential Inputs Positive ADC2 Negative ADC2 1x Gain"] + ADC2_ADC1_20X: [45, "Differential Inputs Positive ADC2 Negative ADC2 20x Gain"] + ADC2_ADC3_1X: [16, "Differential Inputs Positive ADC2 Negative ADC3 1x Gain"] + ADC2_ADC3_20X: [17, "Differential Inputs Positive ADC2 Negative ADC3 20x Gain"] + + ADC3_ADC0_1X: [42, "Differential Inputs Positive ADC3 Negative ADC0 1x Gain"] + ADC3_ADC0_20X: [43, "Differential Inputs Positive ADC3 Negative ADC0 20x Gain"] + ADC3_ADC1_1X: [46, "Differential Inputs Positive ADC3 Negative ADC1 1x Gain"] + ADC3_ADC1_20X: [47, "Differential Inputs Positive ADC3 Negative ADC1 20x Gain"] + ADC3_ADC2_1X: [48, "Differential Inputs Positive ADC3 Negative ADC2 1x Gain"] + ADC3_ADC2_20X: [49, "Differential Inputs Positive ADC3 Negative ADC2 20x Gain"] + ADC3_ADC3_1X: [36, "Differential Inputs Positive ADC3 Negative ADC3 1x Gain"] + ADC3_ADC3_20X: [37, "Differential Inputs Positive ADC3 Negative ADC3 20x Gain"] + ADC3_ADC4_1X: [18, "Differential Inputs Positive ADC4 Negative ADC0 1x Gain"] + ADC3_ADC4_20X: [19, "Differential Inputs Positive ADC4 Negative ADC0 20x Gain"] + ADC3_ADC5_1X: [20, "Differential Inputs Positive ADC5 Negative ADC1 1x Gain"] + ADC3_ADC5_20X: [21, "Differential Inputs Positive ADC5 Negative ADC1 20x Gain"] + ADC3_ADC6_1X: [22, "Differential Inputs Positive ADC6 Negative ADC2 1x Gain"] + ADC3_ADC6_20X: [23, "Differential Inputs Positive ADC6 Negative ADC2 20x Gain"] + ADC3_ADC7_1X: [24, "Differential Inputs Positive ADC7 Negative ADC3 1x Gain"] + ADC3_ADC7_20X: [25, "Differential Inputs Positive ADC7 Negative ADC3 20x Gain"] + + ADC4_ADC3_1X: [50, "Differential Inputs Positive ADC4 Negative ADC3 1x Gain"] + ADC4_ADC3_20X: [51, "Differential Inputs Positive ADC4 Negative ADC3 20x Gain"] + ADC4_ADC5_1X: [26, "Differential Inputs Positive ADC4 Negative ADC5 1x Gain"] + ADC4_ADC5_20X: [27, "Differential Inputs Positive ADC4 Negative ADC5 20x Gain"] + + ADC5_ADC3_1X: [52, "Differential Inputs Positive ADC5 Negative ADC3 1x Gain"] + ADC5_ADC3_20X: [53, "Differential Inputs Positive ADC5 Negative ADC3 20x Gain"] + ADC5_ADC4_1X: [58, "Differential Inputs Positive ADC5 Negative ADC4 1x Gain"] + ADC5_ADC4_20X: [59, "Differential Inputs Positive ADC5 Negative ADC4 20x Gain"] + ADC5_ADC6_1X: [28, "Differential Inputs Positive ADC5 Negative ADC6 1x Gain"] + ADC5_ADC6_20X: [29, "Differential Inputs Positive ADC5 Negative ADC6 20x Gain"] + + ADC6_ADC3_1X: [54, "Differential Inputs Positive ADC6 Negative ADC3 1x Gain"] + ADC6_ADC3_20X: [55, "Differential Inputs Positive ADC6 Negative ADC3 20x Gain"] + ADC6_ADC5_1X: [60, "Differential Inputs Positive ADC6 Negative ADC5 1x Gain"] + ADC6_ADC5_20X: [61, "Differential Inputs Positive ADC6 Negative ADC5 20x Gain"] + ADC6_ADC7_1X: [30, "Differential Inputs Positive ADC6 Negative ADC7 1x Gain"] + ADC6_ADC7_20X: [31, "Differential Inputs Positive ADC6 Negative ADC7 20x Gain"] + + ADC7_ADC3_1X: [56, "Differential Inputs Positive ADC7 Negative ADC3 1x Gain"] + ADC7_ADC3_20X: [57, "Differential Inputs Positive ADC7 Negative ADC3 20x Gain"] + ADC7_ADC6_1X: [62, "Differential Inputs Positive ADC7 Negative ADC6 1x Gain"] + ADC7_ADC6_20X: [63, "Differential Inputs Positive ADC7 Negative ADC6 20x Gain"] + ADC7_ADC7_1X: [38, "Differential Inputs Positive ADC7 Negative ADC7 1x Gain"] + ADC7_ADC7_20X: [39, "Differential Inputs Positive ADC7 Negative ADC7 20x Gain"] + REFS: + _write_constraint: enum + _replace_enum: + VCC: [0, "Vcc used as Voltage Reference, disconnected from Aref"] + AREF: [1, "External Voltage Reference at AREF pin, Internal Voltage Reference turned off"] + INTERNAL: [2, "Internal 1.1V Voltage Reference"] +CPU: + _modify: + OSCCAL: + access: read-write + CLKPR: + CLKPS: + _replace_enum: + PRESCALER_1: [0, "Prescaler Value 1"] + PRESCALER_2: [1, "Prescaler Value 2"] + PRESCALER_4: [2, "Prescaler Value 4"] + PRESCALER_8: [3, "Prescaler Value 8"] + PRESCALER_16: [4, "Prescaler Value 16"] + PRESCALER_32: [5, "Prescaler Value 32"] + PRESCALER_64: [6, "Prescaler Value 64"] + PRESCALER_128: [7, "Prescaler Value 128"] + PRESCALER_256: [8, "Prescaler Value 256"] + MCUCR: + _add: + BODS: + description: "BOD Sleep (available on some devices)" + bitOffset: 7 + bitWidth: 1 + access: read-write + BODSE: + description: "BOD Sleep Enable (available on some devices)" + bitOffset: 2 + bitWidth: 1 + access: read-write + OSCCAL: + _modify: + CAL: + access: read-write +EEPROM: + EECR: + EEPM: + _replace_enum: + ATOMIC: [0, "Atomic (erase and write in one operation)"] + ERASE: [1, "Erase only"] + WRITE: [2, "Write only"] +EXINT: + _modify: + GIFR: + access: read-write + MCUCR: + _delete: + ISC??: + _add: + ISC0: + description: "Interrupt Sense Control 0 bits" + bitOffset: 0 + bitWidth: 2 + access: read-write + ISC0: + _replace_enum: + LOW: [0, "The low level of INTx generates an interrupt request"] + TOGGLE: [1, "Any logical change on INTx generates an interrupt request"] + FALLING: [2, "The falling edge of INTx generates an interrupt request"] + RISING: [3, "The rising edge of INTx generates an interrupt request"] +USI: + _modify: + USISR: + access: read-write + USICR: + _modify: + USICLK: + access: write-only + USITC: + access: write-only + USIWM: + _replace_enum: + DISABLED: [0, "All detectors disabled. Port pins operates as normal."] + THREE_WIRE: [1, "Three-wire mode. Uses DO, DI, and USCK pins."] + TWO_WIRE_SLAVE: [2, "Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."] + TWO_WIRE_MASTER: [3, "Two-wire mode (Master). Uses SDA and SCL pins."] + USICS: + NO_CLOCK: [0, "No Clock/Software clock strobe"] + TC0: [1, "Timer/Counter0 Compare Match"] + EXT_POS: [2, "External, positive edge"] + EXT_NEG: [3, "External, negative edge"] + USISR: + _modify: + USIDC: + access: read-only diff --git a/patch/timer/attiny84.yaml b/patch/timer/attiny84.yaml new file mode 100644 index 0000000..f04b576 --- /dev/null +++ b/patch/timer/attiny84.yaml @@ -0,0 +1,14 @@ +# This intermediate file is needed because peripheral-level includes are not +# supported in top-level files. + +_modify: + TC0: + description: "Timer/Counter0, 8-bit, PWM" + +TC0: + _include: + - "dev/8bit-tiny8n-tc0.yaml" + +TC1: + _include: + - "dev/16bit-tiny84-tc1.yaml" diff --git a/patch/timer/dev/16bit-tiny84-tc1.yaml b/patch/timer/dev/16bit-tiny84-tc1.yaml new file mode 100644 index 0000000..7033632 --- /dev/null +++ b/patch/timer/dev/16bit-tiny84-tc1.yaml @@ -0,0 +1,30 @@ +TCCR?A: + _modify: + COM??: + _write_constraint: enum + COM??: + _replace_enum: + DISCONNECTED: [0, "Normal port operation, OCix disconnected"] + MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] + MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] + MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] + +TCCR?B: + _modify: + CS?: + _write_constraint: enum + CS?: + _replace_enum: + NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] + DIRECT: [1, "Running, No Prescaling"] + PRESCALE_8: [2, "Running, CLK/8"] + PRESCALE_64: [3, "Running, CLK/64"] + PRESCALE_256: [4, "Running, CLK/256"] + PRESCALE_1024: [5, "Running, CLK/1024"] + EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] + EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] + +TCCR?C: + _modify: + FOC??: + access: write-only diff --git a/src/devices/mod.rs b/src/devices/mod.rs index 189e693..2b38408 100644 --- a/src/devices/mod.rs +++ b/src/devices/mod.rs @@ -155,6 +155,25 @@ impl atmega64::Peripherals { } } +/// [ATtiny84](https://www.microchip.com/wwwproducts/en/ATtiny84) +#[cfg(feature = "attiny84")] +pub mod attiny84; + +#[cfg(feature = "attiny84")] +impl attiny84::Peripherals { + /// Returns all the peripherals *once* + #[inline] + pub fn take() -> Option { + crate::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { attiny84::Peripherals::steal() }) + } + }) + } +} + /// [ATtiny85](https://www.microchip.com/wwwproducts/en/ATtiny85) #[cfg(feature = "attiny85")] pub mod attiny85; diff --git a/src/lib.rs b/src/lib.rs index f5a6e2d..62fbe01 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -7,6 +7,7 @@ #![cfg_attr(feature = "atmega32u4", doc = "**atmega32u4**,")] #![cfg_attr(feature = "atmega48p", doc = "**atmega48p**,")] #![cfg_attr(feature = "atmega64", doc = "**atmega64**,")] +#![cfg_attr(feature = "attiny84", doc = "**attiny84**,")] #![cfg_attr(feature = "attiny85", doc = "**attiny85**,")] #![cfg_attr(feature = "attiny88", doc = "**attiny88**,")] //! and a few things which apply to AVR microcontrollers generally. @@ -87,6 +88,8 @@ pub use crate::devices::atmega48p; pub use crate::devices::atmega64; #[cfg(feature = "atmega8")] pub use crate::devices::atmega8; +#[cfg(feature = "attiny84")] +pub use crate::devices::attiny84; #[cfg(feature = "attiny85")] pub use crate::devices::attiny85; #[cfg(feature = "attiny88")] @@ -101,6 +104,7 @@ pub use crate::devices::attiny88; feature = "atmega32u4", feature = "atmega48p", feature = "atmega64", + feature = "attiny84", feature = "attiny85", feature = "attiny88", )))] diff --git a/vendor/attiny84.atdf b/vendor/attiny84.atdf new file mode 100644 index 0000000..1b88466 --- /dev/null +++ b/vendor/attiny84.atdf @@ -0,0 +1,685 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file -- 2.49.0