From f0ea250acb7690c18f366133af3437c6e7d15a19 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?=
 <fandabohacek@gmail.com>
Date: Wed, 21 Dec 2022 01:08:58 +0100
Subject: [PATCH] Patch TCCR0 CS correctly

---
 patch/timer/dev/8bit-mega8.yaml | 8 ++++++++
 vendor/atmega8.atdf             | 4 +++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/patch/timer/dev/8bit-mega8.yaml b/patch/timer/dev/8bit-mega8.yaml
index e2162a1ffed1dca1eafe3e3b5f3483efa1008841..4ae971e608f4a3023f4a7757d2f5d9c0646615dd 100644
--- a/patch/timer/dev/8bit-mega8.yaml
+++ b/patch/timer/dev/8bit-mega8.yaml
@@ -1,4 +1,12 @@
 TCCR?:
+  _delete:
+    - CS00
+    - CS01
+    - CS02
+  _add:
+    CS0:
+      description: "Clock Select 0"
+      bitRange: "[2:0]"
   CS0:
     _replace_enum:
       NO_CLOCK:      [0, "No clock source (Timer/Counter stopped)"]
diff --git a/vendor/atmega8.atdf b/vendor/atmega8.atdf
index ec64a9b36ffbc416d68595fbac32733245673d32..5edc055088aac4d2e49ac18443f6f296591ce541 100644
--- a/vendor/atmega8.atdf
+++ b/vendor/atmega8.atdf
@@ -557,7 +557,9 @@
           <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
         </register>
         <register caption="Timer/Counter0 Control Register" name="TCCR0" offset="0x53" size="1">
-          <bitfield caption="Clock Select0 bit 0" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
+          <bitfield caption="Clock Select0 bit 2" mask="0x04" name="CS02"/>
+          <bitfield caption="Clock Select0 bit 1" mask="0x02" name="CS01"/>
+          <bitfield caption="Clock Select0 bit 0" mask="0x01" name="CS00" values="CLK_SEL_3BIT_EXT"/>
         </register>
         <register caption="Timer Counter 0" name="TCNT0" offset="0x52" size="1" mask="0xFF"/>
       </register-group>