M Cargo.toml => Cargo.toml +1 -0
@@ 25,6 25,7 @@ atmega328p = []
atmega32u4 = []
atmega64 = []
attiny85 = []
+attiny88 = []
rt = ["avr-device-macros"]
[dependencies]
M Makefile => Makefile +1 -1
@@ 1,6 1,6 @@
all: deps chips
-CHIPS := atmega1280 atmega2560 atmega8 atmega328p atmega32u4 atmega64 attiny85
+CHIPS := atmega1280 atmega2560 atmega8 atmega328p atmega32u4 atmega64 attiny85 attiny88
RUSTUP_TOOLCHAIN ?= nightly
M README.md => README.md +1 -0
@@ 18,6 18,7 @@ Via the feature you can select which chip you want the register specifications f
* `atmega32u4`
* `atmega64`
* `attiny85`
+* `attiny88`
## Build Instructions
The version on `crates.io` is pre-built. The following is only necessary when trying to build this crate from source.
A patch/attiny88.yaml => patch/attiny88.yaml +127 -0
@@ 0,0 1,127 @@
+_include:
+ - "common/ac.yaml"
+ - "common/spi.yaml"
+ - "common/wdt.yaml"
+
+ - "timer/attiny88.yaml"
+
+ADC:
+ ADMUX:
+ _modify:
+ MUX:
+ description: "Analog Channel Selection Bits"
+ MUX:
+ _replace_enum:
+ ADC0: [0, "ADC Single Ended Input pin 0"]
+ ADC1: [1, "ADC Single Ended Input pin 1"]
+ ADC2: [2, "ADC Single Ended Input pin 2"]
+ ADC3: [3, "ADC Single Ended Input pin 3"]
+ ADC4: [4, "ADC Single Ended Input pin 4"]
+ ADC5: [5, "ADC Single Ended Input pin 5"]
+ ADC6: [6, "ADC Single Ended Input pin 6"]
+ ADC7: [7, "ADC Single Ended Input pin 7"]
+ TEMPSENS: [8, "Temperature sensor"]
+ ADC_VBG: [14, "Internal Reference (VBG)"]
+ ADC_GND: [15, "0V (GND)"]
+ REFS0:
+ _replace_enum:
+ INTERNAL: [0, "Internal 1.1V Voltage Reference"]
+ AVCC: [1, "AVcc Reference"]
+ ADCSRA:
+ ADPS:
+ _replace_enum:
+ PRESCALER_2: [1, "Prescaler Value 2"]
+ PRESCALER_4: [2, "Prescaler Value 4"]
+ PRESCALER_8: [3, "Prescaler Value 8"]
+ PRESCALER_16: [4, "Prescaler Value 16"]
+ PRESCALER_32: [5, "Prescaler Value 32"]
+ PRESCALER_64: [6, "Prescaler Value 64"]
+ PRESCALER_128: [7, "Prescaler Value 128"]
+ ADCSRB:
+ ADTS:
+ _replace_enum:
+ FREE: [0, "Free Running mode"]
+ AC: [1, "Analog Comparator"]
+ INT0: [2, "External Interrupt Request 0"]
+ TC0_CMA: [3, "Timer/Counter0 Compare Match A"]
+ TC0_OVF: [4, "Timer/Counter0 Overflow"]
+ TC1_CMB: [5, "Timer/Counter1 Compare Match B"]
+ TC1_OVF: [6, "Timer/Counter1 Overflow"]
+ TC1_CE: [7, "Timer/Counter1 Capture Event"]
+CPU:
+ _modify:
+ CLKPR:
+ access: read-write
+ OSCCAL:
+ access: read-write
+ PORTCR:
+ access: read-write
+ PRR:
+ access: read-write
+ CLKPR:
+ CLKPS:
+ _replace_enum:
+ PRESCALER_1: [0, "Prescaler Value 1"]
+ PRESCALER_2: [1, "Prescaler Value 2"]
+ PRESCALER_4: [2, "Prescaler Value 4"]
+ PRESCALER_8: [3, "Prescaler Value 8"]
+ PRESCALER_16: [4, "Prescaler Value 16"]
+ PRESCALER_32: [5, "Prescaler Value 32"]
+ PRESCALER_64: [6, "Prescaler Value 64"]
+ PRESCALER_128: [7, "Prescaler Value 128"]
+ PRESCALER_256: [8, "Prescaler Value 256"]
+ SMCR:
+ SM:
+ _replace_enum:
+ IDLE: [0, "Idle"]
+ ADC: [1, "ADC Noise Reduction"]
+ PDOWN: [2, "Power-down"]
+EEPROM:
+ EECR:
+ EEPM:
+ _replace_enum:
+ ATOMIC: [0, "Atomic (erase and write in one operation)"]
+ ERASE: [1, "Erase only"]
+ WRITE: [2, "Write only"]
+EXINT:
+ EICRA:
+ ISC0:
+ _replace_enum:
+ LOW: [0, "The low level of INT0 generates an interrupt request"]
+ TOGGLE: [1, "Any logical change on INT0 generates an interrupt request"]
+ FALLING: [2, "The falling edge of INT0 generates an interrupt request"]
+ RISING: [3, "The rising edge of INT0 generates an interrupt request"]
+ ISC1:
+ _replace_enum:
+ LOW: [0, "The low level of INT1 generates an interrupt request"]
+ TOGGLE: [1, "Any logical change on INT1 generates an interrupt request"]
+ FALLING: [2, "The falling edge of INT1 generates an interrupt request"]
+ RISING: [3, "The rising edge of INT1 generates an interrupt request"]
+ _modify:
+ PCICR:
+ description: "Pin Change Interrupt Control Register"
+PORTA:
+ _modify:
+ PORTA:
+ access: read-write
+ DDRA:
+ access: read-write
+TWI:
+ TWCR:
+ _modify:
+ TWWC:
+ access: read-only
+ TWAMR:
+ _modify:
+ TWAM:
+ description: "TWI (Slave) Address Mask Bits"
+ TWSR:
+ _modify:
+ TWS:
+ access: read-only
+ TWPS:
+ _replace_enum:
+ PRESCALER_1: [0, "Prescaler Value 1"]
+ PRESCALER_4: [1, "Prescaler Value 4"]
+ PRESCALER_16: [2, "Prescaler Value 16"]
+ PRESCALER_64: [3, "Prescaler Value 64"]
A patch/timer/attiny88.yaml => patch/timer/attiny88.yaml +14 -0
@@ 0,0 1,14 @@
+# This intermediate file is needed because peripheral-level includes are not
+# supported in top-level files.
+
+_modify:
+ TC1:
+ description: "Timer/Counter1, 16-bit, PWM"
+
+TC0:
+ _include:
+ - "dev/8bit-tiny88.yaml"
+
+TC1:
+ _include:
+ - "dev/16bit.yaml"
A patch/timer/dev/8bit-tiny88.yaml => patch/timer/dev/8bit-tiny88.yaml +11 -0
@@ 0,0 1,11 @@
+TCCR?A:
+ CS?:
+ _replace_enum:
+ NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"]
+ DIRECT: [1, "Running, No Prescaling"]
+ PRESCALE_8: [2, "Running, CLK/8"]
+ PRESCALE_64: [3, "Running, CLK/64"]
+ PRESCALE_256: [4, "Running, CLK/256"]
+ PRESCALE_1024: [5, "Running, CLK/1024"]
+ EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"]
+ EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"]
M src/devices/mod.rs => src/devices/mod.rs +19 -0
@@ 135,3 135,22 @@ impl attiny85::Peripherals {
})
}
}
+
+/// [ATtiny88](https://www.microchip.com/wwwproducts/en/ATtiny88)
+#[cfg(feature = "attiny88")]
+pub mod attiny88;
+
+#[cfg(feature = "attiny88")]
+impl attiny88::Peripherals {
+ /// Returns all the peripherals *once*
+ #[inline]
+ pub fn take() -> Option<Self> {
+ crate::interrupt::free(|_| {
+ if unsafe { DEVICE_PERIPHERALS } {
+ None
+ } else {
+ Some(unsafe { attiny88::Peripherals::steal() })
+ }
+ })
+ }
+}
M src/lib.rs => src/lib.rs +5 -0
@@ 6,6 6,7 @@
#![cfg_attr(feature = "atmega32u4", doc = "**atmega32u4**,")]
#![cfg_attr(feature = "atmega64", doc = "**atmega64**,")]
#![cfg_attr(feature = "attiny85", doc = "**attiny85**,")]
+#![cfg_attr(feature = "attiny88", doc = "**attiny88**,")]
//! and a few things which apply to AVR microcontrollers generally.
//!
//! Which chips the crate is built for depends on the feature flag used.
@@ 17,6 18,7 @@
//! * `atmega32u4`
//! * `atmega64`
//! * `attiny85`
+//! * `attiny88`
#![no_std]
#![feature(llvm_asm)]
@@ 78,6 80,8 @@ pub use crate::devices::atmega8;
pub use crate::devices::atmega64;
#[cfg(feature = "attiny85")]
pub use crate::devices::attiny85;
+#[cfg(feature = "attiny88")]
+pub use crate::devices::attiny88;
#[cfg(not(any(
feature = "atmega1280",
@@ 87,5 91,6 @@ pub use crate::devices::attiny85;
feature = "atmega32u4",
feature = "atmega64",
feature = "attiny85",
+ feature = "attiny88",
)))]
compile_error!("You need to select at least one chip as a feature!");
A vendor/attiny88.atdf => vendor/attiny88.atdf +1015 -0
@@ 0,0 1,1015 @@
+<?xml version="1.0" encoding="UTF-8"?><avr-tools-device-file xmlns:xalan="http://xml.apache.org/xalan" xmlns:NumHelper="NumHelper" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+ <variants>
+ <variant ordercode="ATtiny88-MMU" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5" package="QFN28" pinout="QFN28"/>
+ <variant ordercode="ATtiny88-MMH" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5" package="QFN28" pinout="QFN28"/>
+ <variant ordercode="ATtiny88-PU" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5" package="PDIP28" pinout="PDIP"/>
+ <variant ordercode="ATtiny88-AU" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5" package="TQFP32" pinout="TQFP32_QFN32"/>
+ <variant ordercode="ATtiny88-CCU" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5" package="UFBGA32" pinout="UFBGA"/>
+ <variant ordercode="ATtiny88-MU" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5" package="QFN32" pinout="TQFP32_QFN32"/>
+ </variants>
+ <devices>
+ <device name="ATtiny88" architecture="AVR8" family="tinyAVR">
+ <address-spaces>
+ <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
+ <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH" pagesize="0x40"/>
+ </address-space>
+ <address-space endianness="little" name="signatures" id="signatures" start="0" size="3">
+ <memory-segment start="0" size="3" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
+ </address-space>
+ <address-space endianness="little" name="fuses" id="fuses" start="0" size="0x0003">
+ <memory-segment start="0" size="0x0003" type="fuses" rw="RW" exec="0" name="FUSES"/>
+ </address-space>
+ <address-space endianness="little" name="lockbits" id="lockbits" start="0" size="0x0001">
+ <memory-segment start="0" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
+ </address-space>
+ <address-space endianness="little" name="data" id="data" start="0x0000" size="0x0300">
+ <memory-segment external="false" type="regs" size="0x0020" start="0x0000" name="REGISTERS"/>
+ <memory-segment name="MAPPED_IO" start="0x0020" size="0x00e0" type="io" external="false"/>
+ <memory-segment name="IRAM" start="0x0100" size="0x0200" type="ram" external="false"/>
+ </address-space>
+ <address-space endianness="little" name="eeprom" id="eeprom" start="0x0000" size="0x0040">
+ <memory-segment start="0x0000" size="0x0040" type="eeprom" rw="RW" exec="0" name="EEPROM" pagesize="0x04"/>
+ </address-space>
+ <address-space size="0x40" start="0x00" endianness="little" name="io" id="io"/>
+ <address-space endianness="little" name="osccal" id="osccal" start="0" size="1">
+ <memory-segment start="0" size="1" type="osccal" rw="R" exec="0" name="OSCCAL"/>
+ </address-space>
+ </address-spaces>
+ <peripherals>
+ <module name="TC16">
+ <instance name="TC1" caption="Timer/Counter, 16-bit">
+ <register-group name="TC1" name-in-module="TC1" offset="0x00" address-space="data" caption="Timer/Counter, 16-bit"/>
+ <signals>
+ <signal group="T" pad="PD5"/>
+ <signal group="ICP" pad="PB0"/>
+ <signal group="OCA" pad="PB1"/>
+ <signal group="OCB" pad="PB3"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="AC">
+ <instance name="AC" caption="Analog Comparator">
+ <register-group name="AC" name-in-module="AC" offset="0x00" address-space="data" caption="Analog Comparator"/>
+ <signals>
+ <signal group="AIN" index="0" pad="PD6"/>
+ <signal group="AIN" index="1" pad="PD7"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="PORT">
+ <instance name="PORTB" caption="I/O Port">
+ <register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data" caption="I/O Port"/>
+ <signals>
+ <signal group="P" function="default" pad="PB0" index="0"/>
+ <signal group="P" function="default" pad="PB1" index="1"/>
+ <signal group="P" function="default" pad="PB2" index="2"/>
+ <signal group="P" function="default" pad="PB3" index="3"/>
+ <signal group="P" function="default" pad="PB4" index="4"/>
+ <signal group="P" function="default" pad="PB5" index="5"/>
+ <signal group="P" function="default" pad="PB6" index="6"/>
+ <signal group="P" function="default" pad="PB7" index="7"/>
+ </signals>
+ </instance>
+ <instance name="PORTD" caption="I/O Port">
+ <register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data" caption="I/O Port"/>
+ <signals>
+ <signal group="P" function="default" pad="PD0" index="0"/>
+ <signal group="P" function="default" pad="PD1" index="1"/>
+ <signal group="P" function="default" pad="PD2" index="2"/>
+ <signal group="P" function="default" pad="PD3" index="3"/>
+ <signal group="P" function="default" pad="PD4" index="4"/>
+ <signal group="P" function="default" pad="PD5" index="5"/>
+ <signal group="P" function="default" pad="PD6" index="6"/>
+ <signal group="P" function="default" pad="PD7" index="7"/>
+ </signals>
+ </instance>
+ <instance name="PORTC" caption="I/O Port">
+ <register-group name="PORTC" name-in-module="PORTC" offset="0x00" address-space="data" caption="I/O Port"/>
+ <signals>
+ <signal group="P" function="default" pad="PC0" index="0"/>
+ <signal group="P" function="default" pad="PC1" index="1"/>
+ <signal group="P" function="default" pad="PC2" index="2"/>
+ <signal group="P" function="default" pad="PC3" index="3"/>
+ <signal group="P" function="default" pad="PC4" index="4"/>
+ <signal group="P" function="default" pad="PC5" index="5"/>
+ <signal group="P" function="default" pad="PC6" index="6"/>
+ <signal group="P" function="default" pad="PC7" index="7"/>
+ </signals>
+ </instance>
+ <instance name="PORTA" caption="I/O Port">
+ <register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data" caption="I/O Port"/>
+ <signals>
+ <signal group="P" function="default" pad="PA0" index="0"/>
+ <signal group="P" function="default" pad="PA1" index="1"/>
+ <signal group="P" function="default" pad="PA2" index="2"/>
+ <signal group="P" function="default" pad="PA3" index="3"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="SPI">
+ <instance name="SPI" caption="Serial Peripheral Interface">
+ <register-group name="SPI" name-in-module="SPI" offset="0x00" address-space="data" caption="Serial Peripheral Interface"/>
+ <signals>
+ <signal group="SCK" pad="PB5"/>
+ <signal group="MISO" pad="PB4"/>
+ <signal group="MOSI" pad="PB3"/>
+ <signal group="SS" pad="PB2"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="WDT">
+ <instance name="WDT" caption="Watchdog Timer">
+ <register-group name="WDT" name-in-module="WDT" offset="0x00" address-space="data" caption="Watchdog Timer"/>
+ </instance>
+ </module>
+ <module name="TWI">
+ <instance name="TWI" caption="Two Wire Serial Interface">
+ <register-group name="TWI" name-in-module="TWI" offset="0x00" address-space="data" caption="Two Wire Serial Interface"/>
+ <signals>
+ <signal group="SCL" pad="PC6"/>
+ <signal group="SDA" pad="PC5"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="ADC">
+ <instance name="ADC" caption="Analog-to-Digital Converter">
+ <register-group name="ADC" name-in-module="ADC" offset="0x00" address-space="data" caption="Analog-to-Digital Converter"/>
+ <signals>
+ <signal group="ADC" index="0" pad="PC0"/>
+ <signal group="ADC" index="1" pad="PC1"/>
+ <signal group="ADC" index="2" pad="PC2"/>
+ <signal group="ADC" index="3" pad="PC3"/>
+ <signal group="ADC" index="4" pad="PC4"/>
+ <signal group="ADC" index="5" pad="PC5"/>
+ <signal group="ADC" index="6" pad="PA0"/>
+ <signal group="ADC" index="7" pad="PA1"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="EXINT">
+ <instance name="EXINT" caption="External Interrupts">
+ <register-group name="EXINT" name-in-module="EXINT" offset="0x00" address-space="data" caption="External Interrupts"/>
+ <signals>
+ <signal group="PCINT" index="0" pad="PB0"/>
+ <signal group="PCINT" index="1" pad="PB1"/>
+ <signal group="PCINT" index="2" pad="PB2"/>
+ <signal group="PCINT" index="3" pad="PB3"/>
+ <signal group="PCINT" index="4" pad="PB4"/>
+ <signal group="PCINT" index="5" pad="PB5"/>
+ <signal group="PCINT" index="6" pad="PB6"/>
+ <signal group="PCINT" index="7" pad="PB7"/>
+ <signal group="PCINT" index="8" pad="PC0"/>
+ <signal group="PCINT" index="9" pad="PC1"/>
+ <signal group="PCINT" index="10" pad="PC2"/>
+ <signal group="PCINT" index="11" pad="PC3"/>
+ <signal group="PCINT" index="12" pad="PC4"/>
+ <signal group="PCINT" index="13" pad="PC5"/>
+ <signal group="PCINT" index="14" pad="PC6"/>
+ <signal group="PCINT" index="15" pad="PC7"/>
+ <signal group="PCINT" index="16" pad="PD0"/>
+ <signal group="PCINT" index="17" pad="PD1"/>
+ <signal group="PCINT" index="18" pad="PD2"/>
+ <signal group="PCINT" index="19" pad="PD3"/>
+ <signal group="PCINT" index="20" pad="PD4"/>
+ <signal group="PCINT" index="21" pad="PD5"/>
+ <signal group="PCINT" index="22" pad="PD6"/>
+ <signal group="PCINT" index="23" pad="PD7"/>
+ <signal group="PCINT" index="24" pad="PA0"/>
+ <signal group="PCINT" index="25" pad="PA1"/>
+ <signal group="PCINT" index="26" pad="PA2"/>
+ <signal group="PCINT" index="27" pad="PA3"/>
+ <signal group="INT" index="0" pad="PD2"/>
+ <signal group="INT" index="1" pad="PD3"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="TC8">
+ <instance name="TC0" caption="Timer/Counter, 8-bit">
+ <register-group name="TC0" name-in-module="TC0" offset="0x00" address-space="data" caption="Timer/Counter, 8-bit"/>
+ <signals>
+ <signal group="T" pad="PD4"/>
+ </signals>
+ </instance>
+ </module>
+ <module name="CPU">
+ <instance name="CPU" caption="CPU Registers">
+ <register-group name="CPU" name-in-module="CPU" offset="0x00" address-space="data" caption="CPU Registers"/>
+ <parameters>
+ <param name="CORE_VERSION" value="V2"/>
+ <param name="NEW_INSTRUCTIONS" value="lpm rd,z+"/>
+ </parameters></instance>
+ </module>
+ <module name="EEPROM">
+ <instance name="EEPROM" caption="EEPROM">
+ <register-group name="EEPROM" name-in-module="EEPROM" offset="0x00" address-space="data" caption="EEPROM"/>
+ </instance>
+ </module>
+ <module name="FUSE">
+ <instance name="FUSE" caption="Fuses">
+ <register-group name="FUSE" name-in-module="FUSE" offset="0" address-space="fuses" caption="Fuses"/>
+ </instance>
+ </module>
+ <module name="LOCKBIT">
+ <instance name="LOCKBIT" caption="Lockbits">
+ <register-group name="LOCKBIT" name-in-module="LOCKBIT" offset="0" address-space="lockbits" caption="Lockbits"/>
+ </instance>
+ </module>
+ </peripherals>
+ <interrupts>
+ <interrupt index="0" name="RESET" caption="External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"/>
+ <interrupt index="1" name="INT0" caption="External Interrupt Request 0"/>
+ <interrupt index="2" name="INT1" caption="External Interrupt Request 1"/>
+ <interrupt index="3" name="PCINT0" caption="Pin Change Interrupt Request 0"/>
+ <interrupt index="4" name="PCINT1" caption="Pin Change Interrupt Request 1"/>
+ <interrupt index="5" name="PCINT2" caption="Pin Change Interrupt Request 2"/>
+ <interrupt index="6" name="PCINT3" caption="Pin Change Interrupt Request 3"/>
+ <interrupt index="7" name="WDT" caption="Watchdog Time-out Interrupt"/>
+ <interrupt index="8" name="TIMER1_CAPT" caption="Timer/Counter1 Capture Event"/>
+ <interrupt index="9" name="TIMER1_COMPA" caption="Timer/Counter1 Compare Match A"/>
+ <interrupt index="10" name="TIMER1_COMPB" caption="Timer/Counter1 Compare Match B"/>
+ <interrupt index="11" name="TIMER1_OVF" caption="Timer/Counter1 Overflow"/>
+ <interrupt index="12" name="TIMER0_COMPA" caption="TimerCounter0 Compare Match A"/>
+ <interrupt index="13" name="TIMER0_COMPB" caption="TimerCounter0 Compare Match B"/>
+ <interrupt index="14" name="TIMER0_OVF" caption="Timer/Couner0 Overflow"/>
+ <interrupt index="15" name="SPI_STC" caption="SPI Serial Transfer Complete"/>
+ <interrupt index="16" name="ADC" caption="ADC Conversion Complete"/>
+ <interrupt index="17" name="EE_RDY" caption="EEPROM Ready"/>
+ <interrupt index="18" name="ANALOG_COMP" caption="Analog Comparator"/>
+ <interrupt index="19" name="TWI" caption="Two-wire Serial Interface"/>
+ </interrupts>
+ <interfaces>
+ <interface name="ISP" type="isp"/>
+ <interface name="HVPP" type="hvpp"/>
+ <interface name="debugWIRE" type="dw"/>
+ </interfaces>
+ <property-groups>
+ <property-group name="SIGNATURES">
+ <property name="JTAGID" value="0x9311"/>
+ <property name="SIGNATURE0" value="0x1e"/>
+ <property name="SIGNATURE1" value="0x93"/>
+ <property name="SIGNATURE2" value="0x11"/>
+ </property-group>
+ <property-group name="OCD">
+ <property name="OCD_REVISION" value="1"/>
+ <property name="OCD_DATAREG" value="0x31"/>
+ <property name="PROGBASE" value="0x0000"/>
+ </property-group>
+ <property-group name="JTAG_INTERFACE">
+ <property name="ALLOWFULLPAGESTREAM" value="0x00"/>
+ </property-group>
+ <property-group name="ISP_INTERFACE">
+ <property name="IspEnterProgMode_timeout" value="200"/>
+ <property name="IspEnterProgMode_stabDelay" value="100"/>
+ <property name="IspEnterProgMode_cmdexeDelay" value="25"/>
+ <property name="IspEnterProgMode_synchLoops" value="32"/>
+ <property name="IspEnterProgMode_byteDelay" value="0"/>
+ <property name="IspEnterProgMode_pollIndex" value="3"/>
+ <property name="IspEnterProgMode_pollValue" value="0x53"/>
+ <property name="IspLeaveProgMode_preDelay" value="1"/>
+ <property name="IspLeaveProgMode_postDelay" value="1"/>
+ <property name="IspChipErase_eraseDelay" value="45"/>
+ <property name="IspChipErase_pollMethod" value="1"/>
+ <property name="IspProgramFlash_mode" value="0x41"/>
+ <property name="IspProgramFlash_blockSize" value="64"/>
+ <property name="IspProgramFlash_delay" value="10"/>
+ <property name="IspProgramFlash_cmd1" value="0x40"/>
+ <property name="IspProgramFlash_cmd2" value="0x4C"/>
+ <property name="IspProgramFlash_cmd3" value="0x00"/>
+ <property name="IspProgramFlash_pollVal1" value="0x00"/>
+ <property name="IspProgramFlash_pollVal2" value="0x00"/>
+ <property name="IspProgramEeprom_mode" value="0x41"/>
+ <property name="IspProgramEeprom_blockSize" value="4"/>
+ <property name="IspProgramEeprom_delay" value="20"/>
+ <property name="IspProgramEeprom_cmd1" value="0xC1"/>
+ <property name="IspProgramEeprom_cmd2" value="0xC2"/>
+ <property name="IspProgramEeprom_cmd3" value="0x00"/>
+ <property name="IspProgramEeprom_pollVal1" value="0x00"/>
+ <property name="IspProgramEeprom_pollVal2" value="0x00"/>
+ <property name="IspReadFlash_blockSize" value="256"/>
+ <property name="IspReadEeprom_blockSize" value="256"/>
+ <property name="IspReadFuse_pollIndex" value="4"/>
+ <property name="IspReadLock_pollIndex" value="4"/>
+ <property name="IspReadSign_pollIndex" value="4"/>
+ <property name="IspReadOsccal_pollIndex" value="4"/>
+ </property-group>
+ <property-group name="PP_INTERFACE">
+ <property name="PpControlStack" value="0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00"/>
+ <property name="PpEnterProgMode_stabDelay" value="100"/>
+ <property name="PpEnterProgMode_progModeDelay" value="0"/>
+ <property name="PpEnterProgMode_latchCycles" value="5"/>
+ <property name="PpEnterProgMode_toggleVtg" value="1"/>
+ <property name="PpEnterProgMode_powerOffDelay" value="15"/>
+ <property name="PpEnterProgMode_resetDelayMs" value="1"/>
+ <property name="PpEnterProgMode_resetDelayUs" value="0"/>
+ <property name="PpLeaveProgMode_stabDelay" value="15"/>
+ <property name="PpLeaveProgMode_resetDelay" value="15"/>
+ <property name="PpChipErase_pulseWidth" value="0"/>
+ <property name="PpChipErase_pollTimeout" value="10"/>
+ <property name="PpProgramFlash_pollTimeout" value="5"/>
+ <property name="PpProgramFlash_mode" value="0x0D"/>
+ <property name="PpProgramFlash_blockSize" value="256"/>
+ <property name="PpReadFlash_blockSize" value="256"/>
+ <property name="PpProgramEeprom_pollTimeout" value="5"/>
+ <property name="PpProgramEeprom_mode" value="0x05"/>
+ <property name="PpProgramEeprom_blockSize" value="256"/>
+ <property name="PpReadEeprom_blockSize" value="256"/>
+ <property name="PpProgramFuse_pulseWidth" value="0"/>
+ <property name="PpProgramFuse_pollTimeout" value="5"/>
+ <property name="PpProgramLock_pulseWidth" value="0"/>
+ <property name="PpProgramLock_pollTimeout" value="5"/>
+ </property-group>
+ <property-group name="ISP_INTERFACE_STK600">
+ <property name="IspEnterProgMode_timeout" value="200"/>
+ <property name="IspEnterProgMode_stabDelay" value="100"/>
+ <property name="IspEnterProgMode_cmdexeDelay" value="25"/>
+ <property name="IspEnterProgMode_synchLoops" value="32"/>
+ <property name="IspEnterProgMode_byteDelay" value="0"/>
+ <property name="IspEnterProgMode_pollIndex" value="3"/>
+ <property name="IspEnterProgMode_pollValue" value="0x53"/>
+ <property name="IspLeaveProgMode_preDelay" value="1"/>
+ <property name="IspLeaveProgMode_postDelay" value="1"/>
+ <property name="IspChipErase_eraseDelay" value="45"/>
+ <property name="IspChipErase_pollMethod" value="1"/>
+ <property name="IspProgramFlash_mode" value="0x41"/>
+ <property name="IspProgramFlash_blockSize" value="64"/>
+ <property name="IspProgramFlash_delay" value="6"/>
+ <property name="IspProgramFlash_cmd1" value="0x40"/>
+ <property name="IspProgramFlash_cmd2" value="0x4C"/>
+ <property name="IspProgramFlash_cmd3" value="0x00"/>
+ <property name="IspProgramFlash_pollVal1" value="0x00"/>
+ <property name="IspProgramFlash_pollVal2" value="0x00"/>
+ <property name="IspProgramEeprom_mode" value="0x41"/>
+ <property name="IspProgramEeprom_blockSize" value="4"/>
+ <property name="IspProgramEeprom_delay" value="5"/>
+ <property name="IspProgramEeprom_cmd1" value="0xC1"/>
+ <property name="IspProgramEeprom_cmd2" value="0xC2"/>
+ <property name="IspProgramEeprom_cmd3" value="0x00"/>
+ <property name="IspProgramEeprom_pollVal1" value="0x00"/>
+ <property name="IspProgramEeprom_pollVal2" value="0x00"/>
+ <property name="IspReadFlash_blockSize" value="256"/>
+ <property name="IspReadEeprom_blockSize" value="256"/>
+ <property name="IspReadFuse_pollIndex" value="4"/>
+ <property name="IspReadLock_pollIndex" value="4"/>
+ <property name="IspReadSign_pollIndex" value="4"/>
+ <property name="IspReadOsccal_pollIndex" value="4"/>
+ </property-group>
+ <property-group name="PP_INTERFACE_STK600">
+ <property name="PpControlStack" value="0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00"/>
+ <property name="PpEnterProgMode_stabDelay" value="100"/>
+ <property name="PpEnterProgMode_progModeDelay" value="0"/>
+ <property name="PpEnterProgMode_latchCycles" value="5"/>
+ <property name="PpEnterProgMode_toggleVtg" value="1"/>
+ <property name="PpEnterProgMode_powerOffDelay" value="20"/>
+ <property name="PpEnterProgMode_resetDelayMs" value="1"/>
+ <property name="PpEnterProgMode_resetDelayUs" value="0"/>
+ <property name="PpLeaveProgMode_stabDelay" value="15"/>
+ <property name="PpLeaveProgMode_resetDelay" value="15"/>
+ <property name="PpChipErase_pulseWidth" value="0"/>
+ <property name="PpChipErase_pollTimeout" value="10"/>
+ <property name="PpProgramFlash_pollTimeout" value="5"/>
+ <property name="PpProgramFlash_mode" value="0x0D"/>
+ <property name="PpProgramFlash_blockSize" value="256"/>
+ <property name="PpReadFlash_blockSize" value="256"/>
+ <property name="PpProgramEeprom_pollTimeout" value="5"/>
+ <property name="PpProgramEeprom_mode" value="0x05"/>
+ <property name="PpProgramEeprom_blockSize" value="256"/>
+ <property name="PpReadEeprom_blockSize" value="256"/>
+ <property name="PpProgramFuse_pulseWidth" value="0"/>
+ <property name="PpProgramFuse_pollTimeout" value="5"/>
+ <property name="PpProgramLock_pulseWidth" value="0"/>
+ <property name="PpProgramLock_pollTimeout" value="5"/>
+ </property-group>
+ <property-group name="PP_INTERFACE_AVRDRAGON">
+ <property name="PpControlStack" value="0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x0C 0x01 0x00 0x00 0x00 0x00"/>
+ <property name="PpEnterProgMode_stabDelay" value="100"/>
+ <property name="PpEnterProgMode_progModeDelay" value="0"/>
+ <property name="PpEnterProgMode_latchCycles" value="5"/>
+ <property name="PpEnterProgMode_toggleVtg" value="1"/>
+ <property name="PpEnterProgMode_powerOffDelay" value="15"/>
+ <property name="PpEnterProgMode_resetDelayMs" value="1"/>
+ <property name="PpEnterProgMode_resetDelayUs" value="0"/>
+ <property name="PpLeaveProgMode_stabDelay" value="15"/>
+ <property name="PpLeaveProgMode_resetDelay" value="15"/>
+ <property name="PpChipErase_pulseWidth" value="0"/>
+ <property name="PpChipErase_pollTimeout" value="10"/>
+ <property name="PpProgramFlash_pollTimeout" value="5"/>
+ <property name="PpProgramFlash_mode" value="0x0D"/>
+ <property name="PpProgramFlash_blockSize" value="256"/>
+ <property name="PpReadFlash_blockSize" value="256"/>
+ <property name="PpProgramEeprom_pollTimeout" value="5"/>
+ <property name="PpProgramEeprom_mode" value="0x05"/>
+ <property name="PpProgramEeprom_blockSize" value="256"/>
+ <property name="PpReadEeprom_blockSize" value="256"/>
+ <property name="PpProgramFuse_pulseWidth" value="0"/>
+ <property name="PpProgramFuse_pollTimeout" value="5"/>
+ <property name="PpProgramLock_pulseWidth" value="0"/>
+ <property name="PpProgramLock_pollTimeout" value="5"/>
+ </property-group>
+ </property-groups>
+ </device>
+ </devices>
+ <modules>
+ <module caption="Fuses" name="FUSE">
+ <register-group caption="Fuses" name="FUSE">
+ <register caption="" name="EXTENDED" offset="0x02" size="1" initval="0xFF">
+ <bitfield caption="Self Programming enable" mask="0x01" name="SELFPRGEN"/>
+ </register>
+ <register caption="" name="HIGH" offset="0x01" size="1" initval="0xDF">
+ <bitfield caption="Reset Disabled (Enable PC6 as i/o pin)" mask="0x80" name="RSTDISBL"/>
+ <bitfield caption="Debug Wire enable" mask="0x40" name="DWEN"/>
+ <bitfield caption="Serial program downloading (SPI) enabled" mask="0x20" name="SPIEN"/>
+ <bitfield caption="Watch-dog Timer always on" mask="0x10" name="WDTON"/>
+ <bitfield caption="Preserve EEPROM through the Chip Erase cycle" mask="0x08" name="EESAVE"/>
+ <bitfield caption="Brown-out Detector trigger level" mask="0x07" name="BODLEVEL" values="ENUM_BODLEVEL"/>
+ </register>
+ <register caption="" name="LOW" offset="0x00" size="1" initval="0x62">
+ <bitfield caption="Divide clock by 8 internally" mask="0x80" name="CKDIV8"/>
+ <bitfield caption="Clock output on PORTB0" mask="0x40" name="CKOUT"/>
+ <bitfield caption="Select Clock Source" mask="0x3F" name="SUT_CKSEL" values="ENUM_SUT_CKSEL"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="ENUM_SUT_CKSEL">
+ <value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms" name="EXTCLK_6CK_14CK_0MS" value="0x0C"/>
+ <value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms" name="EXTCLK_6CK_14CK_4MS1" value="0x1C"/>
+ <value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms" name="EXTCLK_6CK_14CK_65MS" value="0x2C"/>
+ <value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms" name="INTRCOSC_8MHZ_6CK_14CK_0MS" value="0x0E"/>
+ <value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms" name="INTRCOSC_8MHZ_6CK_14CK_4MS1" value="0x1E"/>
+ <value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; default value" name="INTRCOSC_8MHZ_6CK_14CK_65MS_DEFAULT" value="0x2E"/>
+ <value caption="Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms" name="INTRCOSC_128KHZ_6CK_14CK_0MS" value="0x0F"/>
+ <value caption="Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms" name="INTRCOSC_128KHZ_6CK_14CK_4MS1" value="0x1F"/>
+ <value caption="Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms" name="INTRCOSC_128KHZ_6CK_14CK_65MS" value="0x2F"/>
+ </value-group>
+ <value-group caption="" name="ENUM_BODLEVEL">
+ <value caption="Brown-out detection at VCC=4.3 V" name="4V3" value="0x04"/>
+ <value caption="Brown-out detection at VCC=2.7 V" name="2V7" value="0x05"/>
+ <value caption="Brown-out detection at VCC=1.8 V" name="1V8" value="0x06"/>
+ <value caption="Brown-out detection disabled" name="DISABLED" value="0x07"/>
+ </value-group>
+ </module>
+ <module caption="Lockbits" name="LOCKBIT">
+ <register-group caption="Lockbits" name="LOCKBIT">
+ <register caption="" name="LOCKBIT" offset="0x00" size="1" initval="0xFF">
+ <bitfield caption="Memory Lock" mask="0x03" name="LB" values="ENUM_LB"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="ENUM_LB">
+ <value caption="Further programming and verification disabled" name="PROG_VER_DISABLED" value="0x00"/>
+ <value caption="Further programming disabled" name="PROG_DISABLED" value="0x02"/>
+ <value caption="No memory lock features enabled" name="NO_LOCK" value="0x03"/>
+ </value-group>
+ </module>
+ <module caption="Timer/Counter, 16-bit" name="TC16">
+ <register-group caption="Timer/Counter, 16-bit" name="TC1">
+ <register caption="Timer/Counter Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
+ <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
+ <bitfield caption="Timer/Counter1 Output CompareB Match Interrupt Enable" mask="0x04" name="OCIE1B"/>
+ <bitfield caption="Timer/Counter1 Output CompareA Match Interrupt Enable" mask="0x02" name="OCIE1A"/>
+ <bitfield caption="Timer/Counter1 Overflow Interrupt Enable" mask="0x01" name="TOIE1"/>
+ </register>
+ <register caption="Timer/Counter Interrupt Flag register" name="TIFR1" offset="0x36" size="1" ocd-rw="R">
+ <bitfield caption="Input Capture Flag 1" mask="0x20" name="ICF1"/>
+ <bitfield caption="Output Compare Flag 1B" mask="0x04" name="OCF1B"/>
+ <bitfield caption="Output Compare Flag 1A" mask="0x02" name="OCF1A"/>
+ <bitfield caption="Timer/Counter1 Overflow Flag" mask="0x01" name="TOV1"/>
+ </register>
+ <register caption="Timer/Counter1 Control Register A" name="TCCR1A" offset="0x80" size="1">
+ <bitfield caption="Compare Output Mode 1A, bits" mask="0xC0" name="COM1A"/>
+ <bitfield caption="Compare Output Mode 1B, bits" mask="0x30" name="COM1B"/>
+ <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM1"/>
+ </register>
+ <register caption="Timer/Counter1 Control Register B" name="TCCR1B" offset="0x81" size="1">
+ <bitfield caption="Input Capture 1 Noise Canceler" mask="0x80" name="ICNC1"/>
+ <bitfield caption="Input Capture 1 Edge Select" mask="0x40" name="ICES1"/>
+ <bitfield caption="Waveform Generation Mode" mask="0x18" name="WGM1" lsb="2"/>
+ <bitfield caption="Prescaler source of Timer/Counter 1" mask="0x07" name="CS1" values="CLK_SEL_3BIT_EXT"/>
+ </register>
+ <register caption="Timer/Counter1 Control Register C" name="TCCR1C" offset="0x82" size="1" ocd-rw="">
+ <bitfield caption="" mask="0x80" name="FOC1A"/>
+ <bitfield caption="" mask="0x40" name="FOC1B"/>
+ </register>
+ <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+ <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2" mask="0xFFFF"/>
+ <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2" mask="0xFFFF"/>
+ <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2" mask="0xFFFF"/>
+ <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
+ <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
+ <bitfield caption="Prescaler Reset Timer/Counter1 and Timer/Counter0" mask="0x01" name="PSRSYNC"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="CLK_SEL_3BIT_EXT">
+ <value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
+ <value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
+ <value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
+ <value caption="Running, CLK/64" name="VAL_0x03" value="0x03"/>
+ <value caption="Running, CLK/256" name="VAL_0x04" value="0x04"/>
+ <value caption="Running, CLK/1024" name="VAL_0x05" value="0x05"/>
+ <value caption="Running, ExtClk Tn Falling Edge" name="VAL_0x06" value="0x06"/>
+ <value caption="Running, ExtClk Tn Rising Edge" name="VAL_0x07" value="0x07"/>
+ </value-group>
+ </module>
+ <module caption="Analog Comparator" name="AC">
+ <register-group caption="Analog Comparator" name="AC">
+ <register caption="Analog Comparator Control And Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
+ <bitfield caption="Analog Comparator Disable" mask="0x80" name="ACD"/>
+ <bitfield caption="Analog Comparator Bandgap Select" mask="0x40" name="ACBG"/>
+ <bitfield caption="Analog Compare Output" mask="0x20" name="ACO"/>
+ <bitfield caption="Analog Comparator Interrupt Flag" mask="0x10" name="ACI"/>
+ <bitfield caption="Analog Comparator Interrupt Enable" mask="0x08" name="ACIE"/>
+ <bitfield caption="Analog Comparator Input Capture Enable" mask="0x04" name="ACIC"/>
+ <bitfield caption="Analog Comparator Interrupt Mode Select bits" mask="0x03" name="ACIS" values="ANALOG_COMP_INTERRUPT"/>
+ </register>
+ <register caption="Digital Input Disable Register 1" name="DIDR1" offset="0x7F" size="1">
+ <bitfield caption="AIN1 Digital Input Disable" mask="0x02" name="AIN1D"/>
+ <bitfield caption="AIN0 Digital Input Disable" mask="0x01" name="AIN0D"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="ANALOG_COMP_INTERRUPT">
+ <value caption="Interrupt on Toggle" name="VAL_0x00" value="0x00"/>
+ <value caption="Reserved" name="VAL_0x01" value="0x01"/>
+ <value caption="Interrupt on Falling Edge" name="VAL_0x02" value="0x02"/>
+ <value caption="Interrupt on Rising Edge" name="VAL_0x03" value="0x03"/>
+ </value-group>
+ </module>
+ <module caption="I/O Port" name="PORT">
+ <register-group caption="I/O Port" name="PORTB">
+ <register caption="Port B Data Register" name="PORTB" offset="0x25" size="1" mask="0xFF"/>
+ <register caption="Port B Data Direction Register" name="DDRB" offset="0x24" size="1" mask="0xFF"/>
+ <register caption="Port B Input Pins" name="PINB" offset="0x23" size="1" mask="0xFF" ocd-rw="R"/>
+ </register-group>
+ <register-group caption="I/O Port" name="PORTD">
+ <register caption="Port D Data Register" name="PORTD" offset="0x2B" size="1" mask="0xFF"/>
+ <register caption="Port D Data Direction Register" name="DDRD" offset="0x2A" size="1" mask="0xFF"/>
+ <register caption="Port D Input Pins" name="PIND" offset="0x29" size="1" mask="0xFF" ocd-rw="R"/>
+ </register-group>
+ <register-group caption="I/O Port" name="PORTC">
+ <register caption="Port C Data Register" name="PORTC" offset="0x28" size="1" mask="0xFF"/>
+ <register caption="Port C Data Direction Register" name="DDRC" offset="0x27" size="1" mask="0xFF"/>
+ <register caption="Port C Input Pins" name="PINC" offset="0x26" size="1" mask="0xFF" ocd-rw="R"/>
+ </register-group>
+ <register-group caption="I/O Port" name="PORTA">
+ <register caption="Port A Data Register" name="PORTA" offset="0x2E" size="1" mask="0x0F" ocd-rw="R"/>
+ <register caption="Port A Data Direction Register" name="DDRA" offset="0x2D" size="1" mask="0x0F" ocd-rw="R"/>
+ <register caption="Port A Input Pins" name="PINA" offset="0x2C" size="1" mask="0x0F" ocd-rw="R"/>
+ </register-group>
+ </module>
+ <module caption="Serial Peripheral Interface" name="SPI">
+ <register-group caption="Serial Peripheral Interface" name="SPI">
+ <register caption="SPI Data Register" name="SPDR" offset="0x4E" size="1" mask="0xFF" ocd-rw=""/>
+ <register caption="SPI Status Register" name="SPSR" offset="0x4D" size="1" ocd-rw="R">
+ <bitfield caption="SPI Interrupt Flag" mask="0x80" name="SPIF"/>
+ <bitfield caption="Write Collision Flag" mask="0x40" name="WCOL"/>
+ <bitfield caption="Double SPI Speed Bit" mask="0x01" name="SPI2X"/>
+ </register>
+ <register caption="SPI Control Register" name="SPCR" offset="0x4C" size="1">
+ <bitfield caption="SPI Interrupt Enable" mask="0x80" name="SPIE"/>
+ <bitfield caption="SPI Enable" mask="0x40" name="SPE"/>
+ <bitfield caption="Data Order" mask="0x20" name="DORD"/>
+ <bitfield caption="Master/Slave Select" mask="0x10" name="MSTR"/>
+ <bitfield caption="Clock polarity" mask="0x08" name="CPOL"/>
+ <bitfield caption="Clock Phase" mask="0x04" name="CPHA"/>
+ <bitfield caption="SPI Clock Rate Selects" mask="0x03" name="SPR" values="COMM_SCK_RATE_3BIT"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="COMM_SCK_RATE_3BIT">
+ <value caption="fosc/4" name="VAL_0x00" value="0x00"/>
+ <value caption="fosc/16" name="VAL_0x01" value="0x01"/>
+ <value caption="fosc/64" name="VAL_0x02" value="0x02"/>
+ <value caption="fosc/128" name="VAL_0x03" value="0x03"/>
+ <value caption="fosc/2" name="VAL_0x04" value="0x04"/>
+ <value caption="fosc/8" name="VAL_0x05" value="0x05"/>
+ <value caption="fosc/32" name="VAL_0x06" value="0x06"/>
+ <value caption="fosc/64" name="VAL_0x07" value="0x07"/>
+ </value-group>
+ </module>
+ <module caption="Watchdog Timer" name="WDT">
+ <register-group caption="Watchdog Timer" name="WDT">
+ <register caption="Watchdog Timer Control Register" name="WDTCSR" offset="0x60" size="1" ocd-rw="R">
+ <bitfield caption="Watchdog Timeout Interrupt Flag" mask="0x80" name="WDIF"/>
+ <bitfield caption="Watchdog Timeout Interrupt Enable" mask="0x40" name="WDIE"/>
+ <bitfield caption="Watchdog Timer Prescaler Bits" mask="0x27" name="WDP" values="WDOG_TIMER_PRESCALE_4BITS"/>
+ <bitfield caption="Watchdog Change Enable" mask="0x10" name="WDCE"/>
+ <bitfield caption="Watch Dog Enable" mask="0x08" name="WDE"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="WDOG_TIMER_PRESCALE_4BITS">
+ <value caption="Oscillator Cycles 2K" name="VAL_0x00" value="0x00"/>
+ <value caption="Oscillator Cycles 4K" name="VAL_0x01" value="0x01"/>
+ <value caption="Oscillator Cycles 8K" name="VAL_0x02" value="0x02"/>
+ <value caption="Oscillator Cycles 16K" name="VAL_0x03" value="0x03"/>
+ <value caption="Oscillator Cycles 32K" name="VAL_0x04" value="0x04"/>
+ <value caption="Oscillator Cycles 64K" name="VAL_0x05" value="0x05"/>
+ <value caption="Oscillator Cycles 128K" name="VAL_0x06" value="0x06"/>
+ <value caption="Oscillator Cycles 256K" name="VAL_0x07" value="0x07"/>
+ <value caption="Oscillator Cycles 512K" name="VAL_0x08" value="0x08"/>
+ <value caption="Oscillator Cycles 1024K" name="VAL_0x09" value="0x09"/>
+ </value-group>
+ </module>
+ <module caption="Two Wire Serial Interface" name="TWI">
+ <register-group caption="Two Wire Serial Interface" name="TWI">
+ <register caption="TWHSR" name="TWHSR" offset="0xBE" size="1">
+ <bitfield caption="" mask="0x01" name="TWHS"/>
+ </register>
+ <register caption="TWI (Slave) Address Mask Register" name="TWAMR" offset="0xBD" size="1">
+ <bitfield caption="" mask="0xFE" name="TWAM"/>
+ </register>
+ <register caption="TWI Bit Rate register" name="TWBR" offset="0xB8" size="1" mask="0xFF"/>
+ <register caption="TWI Control Register" name="TWCR" offset="0xBC" size="1">
+ <bitfield caption="TWI Interrupt Flag" mask="0x80" name="TWINT"/>
+ <bitfield caption="TWI Enable Acknowledge Bit" mask="0x40" name="TWEA"/>
+ <bitfield caption="TWI Start Condition Bit" mask="0x20" name="TWSTA"/>
+ <bitfield caption="TWI Stop Condition Bit" mask="0x10" name="TWSTO"/>
+ <bitfield caption="TWI Write Collition Flag" mask="0x08" name="TWWC"/>
+ <bitfield caption="TWI Enable Bit" mask="0x04" name="TWEN"/>
+ <bitfield caption="TWI Interrupt Enable" mask="0x01" name="TWIE"/>
+ </register>
+ <register caption="TWI Status Register" name="TWSR" offset="0xB9" size="1">
+ <bitfield caption="TWI Status" mask="0xF8" name="TWS" lsb="3"/>
+ <bitfield caption="TWI Prescaler" mask="0x03" name="TWPS" values="COMM_TWI_PRESACLE"/>
+ </register>
+ <register caption="TWI Data register" name="TWDR" offset="0xBB" size="1" mask="0xFF"/>
+ <register caption="TWI (Slave) Address register" name="TWAR" offset="0xBA" size="1">
+ <bitfield caption="TWI (Slave) Address register Bits" mask="0xFE" name="TWA"/>
+ <bitfield caption="TWI General Call Recognition Enable Bit" mask="0x01" name="TWGCE"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="COMM_TWI_PRESACLE">
+ <value caption="1" name="VAL_0x00" value="0x00"/>
+ <value caption="4" name="VAL_0x01" value="0x01"/>
+ <value caption="16" name="VAL_0x02" value="0x02"/>
+ <value caption="64" name="VAL_0x03" value="0x03"/>
+ </value-group>
+ </module>
+ <module caption="Analog-to-Digital Converter" name="ADC">
+ <register-group caption="Analog-to-Digital Converter" name="ADC">
+ <register caption="The ADC multiplexer Selection Register" name="ADMUX" offset="0x7C" size="1">
+ <bitfield caption="Reference Selection Bit 0" mask="0x40" name="REFS0" values="ANALOG_ADC_V_REF7"/>
+ <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
+ <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x0F" name="MUX"/>
+ </register>
+ <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+ <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1">
+ <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
+ <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
+ <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
+ <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
+ <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
+ <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS" values="ANALOG_ADC_PRESCALER"/>
+ </register>
+ <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
+ <bitfield caption="" mask="0x40" name="ACME"/>
+ <bitfield caption="ADC Auto Trigger Source bits" mask="0x07" name="ADTS" values="ANALOG_ADC_AUTO_TRIGGER"/>
+ </register>
+ <register caption="Digital Input Disable Register 1" name="DIDR1" offset="0x7F" size="1">
+ <bitfield caption="" mask="0x02" name="AIN1D"/>
+ <bitfield caption="" mask="0x01" name="AIN0D"/>
+ </register>
+ <register caption="Digital Input Disable Register 0" name="DIDR0" offset="0x7E" size="1">
+ <bitfield caption="" mask="0x80" name="ADC7D"/>
+ <bitfield caption="" mask="0x40" name="ADC6D"/>
+ <bitfield caption="" mask="0x20" name="ADC5D"/>
+ <bitfield caption="" mask="0x10" name="ADC4D"/>
+ <bitfield caption="" mask="0x08" name="ADC3D"/>
+ <bitfield caption="" mask="0x04" name="ADC2D"/>
+ <bitfield caption="" mask="0x02" name="ADC1D"/>
+ <bitfield caption="" mask="0x01" name="ADC0D"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="ANALOG_ADC_V_REF7">
+ <value caption="Internal 1.1V Voltage Reference" name="VAL_0x00" value="0x00"/>
+ <value caption="AVcc Reference" name="VAL_0x01" value="0x01"/>
+ </value-group>
+ <value-group caption="" name="ANALOG_ADC_PRESCALER">
+ <value caption="2" name="VAL_0x00" value="0x00"/>
+ <value caption="2" name="VAL_0x01" value="0x01"/>
+ <value caption="4" name="VAL_0x02" value="0x02"/>
+ <value caption="8" name="VAL_0x03" value="0x03"/>
+ <value caption="16" name="VAL_0x04" value="0x04"/>
+ <value caption="32" name="VAL_0x05" value="0x05"/>
+ <value caption="64" name="VAL_0x06" value="0x06"/>
+ <value caption="128" name="VAL_0x07" value="0x07"/>
+ </value-group>
+ <value-group caption="" name="ANALOG_ADC_AUTO_TRIGGER">
+ <value caption="Free Running mode" name="VAL_0x00" value="0x00"/>
+ <value caption="Analog Comparator" name="VAL_0x01" value="0x01"/>
+ <value caption="External Interrupt Request 0" name="VAL_0x02" value="0x02"/>
+ <value caption="Timer/Counter0 Compare Match A" name="VAL_0x03" value="0x03"/>
+ <value caption="Timer/Counter0 Overflow" name="VAL_0x04" value="0x04"/>
+ <value caption="Timer/Counter1 Compare Match B" name="VAL_0x05" value="0x05"/>
+ <value caption="Timer/Counter1 Overflow" name="VAL_0x06" value="0x06"/>
+ <value caption="Timer/Counter1 Capture Event" name="VAL_0x07" value="0x07"/>
+ </value-group>
+ </module>
+ <module caption="External Interrupts" name="EXINT">
+ <register-group caption="External Interrupts" name="EXINT">
+ <register caption="External Interrupt Control Register" name="EICRA" offset="0x69" size="1">
+ <bitfield caption="External Interrupt Sense Control 1 Bits" mask="0x0C" name="ISC1" values="INTERRUPT_SENSE_CONTROL2"/>
+ <bitfield caption="External Interrupt Sense Control 0 Bits" mask="0x03" name="ISC0" values="INTERRUPT_SENSE_CONTROL2"/>
+ </register>
+ <register caption="External Interrupt Mask Register" name="EIMSK" offset="0x3D" size="1">
+ <bitfield caption="External Interrupt Request 1 Enable" mask="0x03" name="INT"/>
+ </register>
+ <register caption="External Interrupt Flag Register" name="EIFR" offset="0x3C" size="1" ocd-rw="R">
+ <bitfield caption="External Interrupt Flags" mask="0x03" name="INTF"/>
+ </register>
+ <register caption="" name="PCICR" offset="0x68" size="1">
+ <bitfield caption="" mask="0x0F" name="PCIE"/>
+ </register>
+ <register caption="Pin Change Mask Register 3" name="PCMSK3" offset="0x6A" size="1">
+ <bitfield caption="Pin Change Enable Masks" mask="0x0F" name="PCINT" lsb="24"/>
+ </register>
+ <register caption="Pin Change Mask Register 2" name="PCMSK2" offset="0x6D" size="1">
+ <bitfield caption="Pin Change Enable Masks" mask="0xFF" name="PCINT" lsb="16"/>
+ </register>
+ <register caption="Pin Change Mask Register 1" name="PCMSK1" offset="0x6C" size="1">
+ <bitfield caption="Pin Change Enable Masks" mask="0xFF" name="PCINT" lsb="8"/>
+ </register>
+ <register caption="Pin Change Mask Register 0" name="PCMSK0" offset="0x6B" size="1">
+ <bitfield caption="Pin Change Enable Masks" mask="0xFF" name="PCINT"/>
+ </register>
+ <register caption="Pin Change Interrupt Flag Register" name="PCIFR" offset="0x3B" size="1" ocd-rw="R">
+ <bitfield caption="Pin Change Interrupt Flags" mask="0x0F" name="PCIF"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="INTERRUPT_SENSE_CONTROL2">
+ <value caption="Low Level of INTX" name="VAL_0x00" value="0x00"/>
+ <value caption="Any Logical Change in INTX" name="VAL_0x01" value="0x01"/>
+ <value caption="Falling Edge of INTX" name="VAL_0x02" value="0x02"/>
+ <value caption="Rising Edge of INTX" name="VAL_0x03" value="0x03"/>
+ </value-group>
+ </module>
+ <module caption="Timer/Counter, 8-bit" name="TC8">
+ <register-group caption="Timer/Counter, 8-bit" name="TC0">
+ <register caption="Timer/Counter0 Output Compare Register" name="OCR0B" offset="0x48" size="1" mask="0xFF"/>
+ <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x47" size="1" mask="0xFF"/>
+ <register caption="Timer/Counter0" name="TCNT0" offset="0x46" size="1" mask="0xFF"/>
+ <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x45" size="1">
+ <bitfield caption="Clear Timer on Compare Match" mask="0x08" name="CTC0"/>
+ <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
+ </register>
+ <register caption="Timer/Counter0 Interrupt Mask Register" name="TIMSK0" offset="0x6E" size="1">
+ <bitfield caption="Timer/Counter0 Output Compare Match B Interrupt Enable" mask="0x04" name="OCIE0B"/>
+ <bitfield caption="Timer/Counter0 Output Compare Match A Interrupt Enable" mask="0x02" name="OCIE0A"/>
+ <bitfield caption="Timer/Counter0 Overflow Interrupt Enable" mask="0x01" name="TOIE0"/>
+ </register>
+ <register caption="Timer/Counter0 Interrupt Flag register" name="TIFR0" offset="0x35" size="1" ocd-rw="R">
+ <bitfield caption="Timer/Counter0 Output Compare Flag 0B" mask="0x04" name="OCF0B"/>
+ <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
+ <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
+ </register>
+ <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
+ <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
+ <bitfield caption="Prescaler Reset Timer/Counter1 and Timer/Counter0" mask="0x01" name="PSRSYNC"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="CLK_SEL_3BIT_EXT">
+ <value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
+ <value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
+ <value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
+ <value caption="Running, CLK/64" name="VAL_0x03" value="0x03"/>
+ <value caption="Running, CLK/256" name="VAL_0x04" value="0x04"/>
+ <value caption="Running, CLK/1024" name="VAL_0x05" value="0x05"/>
+ <value caption="Running, ExtClk Tn Falling Edge" name="VAL_0x06" value="0x06"/>
+ <value caption="Running, ExtClk Tn Rising Edge" name="VAL_0x07" value="0x07"/>
+ </value-group>
+ </module>
+ <module caption="CPU Registers" name="CPU">
+ <register-group caption="CPU Registers" name="CPU">
+ <register caption="Power Reduction Register" name="PRR" offset="0x64" size="1" ocd-rw="R">
+ <bitfield caption="Power Reduction TWI" mask="0x80" name="PRTWI"/>
+ <bitfield caption="Power Reduction Timer/Counter0" mask="0x20" name="PRTIM0"/>
+ <bitfield caption="Power Reduction Timer/Counter1" mask="0x08" name="PRTIM1"/>
+ <bitfield caption="Power Reduction Serial Peripheral Interface" mask="0x04" name="PRSPI"/>
+ <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
+ </register>
+ <register caption="Oscillator Calibration Value" name="OSCCAL" offset="0x66" size="1" mask="0xFF" ocd-rw="R">
+ <bitfield caption="Oscillator Calibration " mask="0xFF" name="OSCCAL"/>
+ </register>
+ <register caption="Clock Prescale Register" name="CLKPR" offset="0x61" size="1" ocd-rw="R">
+ <bitfield caption="Clock Prescaler Change Enable" mask="0x80" name="CLKPCE"/>
+ <bitfield caption="Clock Prescaler Select Bits" mask="0x0F" name="CLKPS" values="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
+ </register>
+ <register caption="Status Register" name="SREG" offset="0x5F" size="1">
+ <bitfield caption="Global Interrupt Enable" mask="0x80" name="I"/>
+ <bitfield caption="Bit Copy Storage" mask="0x40" name="T"/>
+ <bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
+ <bitfield caption="Sign Bit" mask="0x10" name="S"/>
+ <bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
+ <bitfield caption="Negative Flag" mask="0x04" name="N"/>
+ <bitfield caption="Zero Flag" mask="0x02" name="Z"/>
+ <bitfield caption="Carry Flag" mask="0x01" name="C"/>
+ </register>
+ <register caption="Stack Pointer Low" name="SPL" offset="0x5D" size="1" mask="0xFF"/>
+ <register caption="Stack Pointer High" name="SPH" offset="0x5E" size="1" mask="0x03"/>
+ <register caption="Store Program Memory Control Register" name="SPMCSR" offset="0x57" size="1">
+ <bitfield caption="Read-While-Write Section Busy" mask="0x40" name="RWWSB"/>
+ <bitfield caption="Clear Temporary Page Buffer" mask="0x10" name="CTPB"/>
+ <bitfield caption="Read Fuse and Lock Bits" mask="0x08" name="RFLB"/>
+ <bitfield caption="Page Write" mask="0x04" name="PGWRT"/>
+ <bitfield caption="Page Erase" mask="0x02" name="PGERS"/>
+ <bitfield caption="Self Programming Enable" mask="0x01" name="SELFPRGEN"/>
+ </register>
+ <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
+ <bitfield caption="BOD Sleep" mask="0x40" name="BODS"/>
+ <bitfield caption="BOD Sleep Enable" mask="0x20" name="BODSE"/>
+ <bitfield caption="Pull-up Disable" mask="0x10" name="PUD"/>
+ </register>
+ <register caption="MCU Status Register" name="MCUSR" offset="0x54" size="1">
+ <bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
+ <bitfield caption="Brown-out Reset Flag" mask="0x04" name="BORF"/>
+ <bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
+ <bitfield caption="Power-on reset flag" mask="0x01" name="PORF"/>
+ </register>
+ <register caption="Sleep Mode Control Register" name="SMCR" offset="0x53" size="1">
+ <bitfield caption="Sleep Mode" mask="0x06" name="SM" values="CPU_SLEEP_MODE_3BITS2"/>
+ <bitfield caption="Sleep Enable" mask="0x01" name="SE"/>
+ </register>
+ <register caption="General Purpose I/O Register 2" name="GPIOR2" offset="0x4B" size="1" mask="0xFF"/>
+ <register caption="General Purpose I/O Register 1" name="GPIOR1" offset="0x4A" size="1" mask="0xFF"/>
+ <register caption="General Purpose I/O Register 0" name="GPIOR0" offset="0x3E" size="1" mask="0xFF"/>
+ <register caption="Port Configuration Register" name="PORTCR" offset="0x32" size="1" ocd-rw="R">
+ <bitfield caption="" mask="0x80" name="BBMD"/>
+ <bitfield caption="" mask="0x40" name="BBMC"/>
+ <bitfield caption="" mask="0x20" name="BBMB"/>
+ <bitfield caption="" mask="0x10" name="BBMA"/>
+ <bitfield caption="" mask="0x08" name="PUDD"/>
+ <bitfield caption="" mask="0x04" name="PUDC"/>
+ <bitfield caption="" mask="0x02" name="PUDB"/>
+ <bitfield caption="" mask="0x01" name="PUDA"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="CPU_CLK_PRESCALE_4_BITS_SMALL">
+ <value caption="1" name="VAL_0x00" value="0x00"/>
+ <value caption="2" name="VAL_0x01" value="0x01"/>
+ <value caption="4" name="VAL_0x02" value="0x02"/>
+ <value caption="8" name="VAL_0x03" value="0x03"/>
+ <value caption="16" name="VAL_0x04" value="0x04"/>
+ <value caption="32" name="VAL_0x05" value="0x05"/>
+ <value caption="64" name="VAL_0x06" value="0x06"/>
+ <value caption="128" name="VAL_0x07" value="0x07"/>
+ <value caption="256" name="VAL_0x08" value="0x08"/>
+ </value-group>
+ <value-group caption="" name="CPU_SLEEP_MODE_3BITS2">
+ <value caption="Idle" name="IDLE" value="0x00"/>
+ <value caption="ADC Noise Reduction (If Available)" name="ADC" value="0x01"/>
+ <value caption="Power Down" name="PDOWN" value="0x02"/>
+ <value caption="Power Save" name="PSAVE" value="0x03"/>
+ <value caption="Reserved" name="VAL_0x04" value="0x04"/>
+ <value caption="Reserved" name="VAL_0x05" value="0x05"/>
+ <value caption="Reserved" name="VAL_0x06" value="0x06"/>
+ <value caption="Reserved" name="VAL_0x07" value="0x07"/>
+ </value-group>
+ <value-group caption="Oscillator Calibration Values" name="OSCCAL_VALUE_ADDRESSES">
+ <value value="0x00" caption="8.0 MHz" name="8_0_MHz"/>
+ </value-group>
+
+ </module>
+ <module caption="EEPROM" name="EEPROM">
+ <register-group caption="EEPROM" name="EEPROM">
+ <register caption="EEPROM Address Register Low Byte" name="EEARL" offset="0x41" size="1" mask="0x3F"/>
+ <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
+ <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
+ <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
+ <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
+ <bitfield caption="EEPROM Master Write Enable" mask="0x04" name="EEMPE"/>
+ <bitfield caption="EEPROM Write Enable" mask="0x02" name="EEPE"/>
+ <bitfield caption="EEPROM Read Enable" mask="0x01" name="EERE"/>
+ </register>
+ </register-group>
+ <value-group caption="" name="EEP_MODE">
+ <value caption="Erase and Write in one operation" name="VAL_0x00" value="0x00"/>
+ <value caption="Erase Only" name="VAL_0x01" value="0x01"/>
+ <value caption="Write Only" name="VAL_0x02" value="0x02"/>
+ </value-group>
+ </module>
+ </modules>
+ <pinouts>
+ <pinout name="TQFP32_QFN32">
+ <pin pad="PD3" position="1"/>
+ <pin pad="PD4" position="2"/>
+ <pin pad="PA2" position="3"/>
+ <pin pad="VCC" position="4"/>
+ <pin pad="GND" position="5"/>
+ <pin pad="PA3" position="6"/>
+ <pin pad="PB6" position="7"/>
+ <pin pad="PB7" position="8"/>
+ <pin pad="PD5" position="9"/>
+ <pin pad="PD6" position="10"/>
+ <pin pad="PD7" position="11"/>
+ <pin pad="PB0" position="12"/>
+ <pin pad="PB1" position="13"/>
+ <pin pad="PB2" position="14"/>
+ <pin pad="PB3" position="15"/>
+ <pin pad="PB4" position="16"/>
+ <pin pad="PB5" position="17"/>
+ <pin pad="AVCC" position="18"/>
+ <pin pad="PA0" position="19"/>
+ <pin pad="PC7" position="20"/>
+ <pin pad="GND" position="21"/>
+ <pin pad="PA1" position="22"/>
+ <pin pad="PC0" position="23"/>
+ <pin pad="PC1" position="24"/>
+ <pin pad="PC2" position="25"/>
+ <pin pad="PC3" position="26"/>
+ <pin pad="PC4" position="27"/>
+ <pin pad="PC5" position="28"/>
+ <pin pad="PC6" position="29"/>
+ <pin pad="PD0" position="30"/>
+ <pin pad="PD1" position="31"/>
+ <pin pad="PD2" position="32"/>
+ </pinout>
+ <pinout name="PDIP">
+ <pin pad="PC6" position="1"/>
+ <pin pad="PD0" position="2"/>
+ <pin pad="PD1" position="3"/>
+ <pin pad="PD2" position="4"/>
+ <pin pad="PD3" position="5"/>
+ <pin pad="PD4" position="6"/>
+ <pin pad="VCC" position="7"/>
+ <pin pad="GND" position="8"/>
+ <pin pad="PB6" position="9"/>
+ <pin pad="PB7" position="10"/>
+ <pin pad="PD5" position="11"/>
+ <pin pad="PD6" position="12"/>
+ <pin pad="PD7" position="13"/>
+ <pin pad="PB0" position="14"/>
+ <pin pad="PB1" position="15"/>
+ <pin pad="PB2" position="16"/>
+ <pin pad="PB3" position="17"/>
+ <pin pad="PB4" position="18"/>
+ <pin pad="PB5" position="19"/>
+ <pin pad="AVCC" position="20"/>
+ <pin pad="PC7" position="21"/>
+ <pin pad="GND" position="22"/>
+ <pin pad="PC0" position="23"/>
+ <pin pad="PC1" position="24"/>
+ <pin pad="PC2" position="25"/>
+ <pin pad="PC3" position="26"/>
+ <pin pad="PC4" position="27"/>
+ <pin pad="PC5" position="28"/>
+ </pinout>
+ <pinout name="QFN28">
+ <pin pad="PD3" position="1"/>
+ <pin pad="PD4" position="2"/>
+ <pin pad="VCC" position="3"/>
+ <pin pad="GND" position="4"/>
+ <pin pad="PB6" position="5"/>
+ <pin pad="PB7" position="6"/>
+ <pin pad="PD5" position="7"/>
+ <pin pad="PD6" position="8"/>
+ <pin pad="PD7" position="9"/>
+ <pin pad="PB0" position="10"/>
+ <pin pad="PB1" position="11"/>
+ <pin pad="PB2" position="12"/>
+ <pin pad="PB3" position="13"/>
+ <pin pad="PB4" position="14"/>
+ <pin pad="PB5" position="15"/>
+ <pin pad="AVCC" position="16"/>
+ <pin pad="PC7" position="17"/>
+ <pin pad="GND" position="18"/>
+ <pin pad="PC0" position="19"/>
+ <pin pad="PC1" position="20"/>
+ <pin pad="PC2" position="21"/>
+ <pin pad="PC3" position="22"/>
+ <pin pad="PC4" position="23"/>
+ <pin pad="PC5" position="24"/>
+ <pin pad="PC6" position="25"/>
+ <pin pad="PD0" position="26"/>
+ <pin pad="PD1" position="27"/>
+ <pin pad="PD2" position="28"/>
+ </pinout>
+ <pinout name="UFBGA">
+ <pin pad="PD2" position="A1"/>
+ <pin pad="PD3" position="B1"/>
+ <pin pad="GND" position="C1"/>
+ <pin pad="VCC" position="D1"/>
+ <pin pad="PB6" position="E1"/>
+ <pin pad="PB7" position="F1"/>
+ <pin pad="PD1" position="A2"/>
+ <pin pad="PD4" position="B2"/>
+ <pin pad="PA2" position="C2"/>
+ <pin pad="PA3" position="D2"/>
+ <pin pad="PD6" position="E2"/>
+ <pin pad="PD5" position="F2"/>
+ <pin pad="PC6" position="A3"/>
+ <pin pad="PD0" position="B3"/>
+ <pin pad="PB0" position="E3"/>
+ <pin pad="PD7" position="F3"/>
+ <pin pad="PC4" position="A4"/>
+ <pin pad="PC5" position="B4"/>
+ <pin pad="PB2" position="E4"/>
+ <pin pad="PB1" position="F4"/>
+ <pin pad="PC2" position="A5"/>
+ <pin pad="PC3" position="B5"/>
+ <pin pad="PA1" position="C5"/>
+ <pin pad="PC7" position="D5"/>
+ <pin pad="AVCC" position="E5"/>
+ <pin pad="PB3" position="F5"/>
+ <pin pad="PC1" position="A6"/>
+ <pin pad="PC0" position="B6"/>
+ <pin pad="GND" position="C6"/>
+ <pin pad="PA0" position="D6"/>
+ <pin pad="PB5" position="E6"/>
+ <pin pad="PB4" position="F6"/>
+ </pinout>
+ </pinouts>
+</avr-tools-device-file><
\ No newline at end of file