From 8be91f55956952f89e4ceb71847fafa51ed6f835 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Fri, 23 Dec 2022 23:20:16 +0100 Subject: [PATCH] Split WGM2 to WGM21, WGM20 --- patch/timer/dev/8bit-async-mega8.yaml | 12 ------------ vendor/atmega8.atdf | 3 ++- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/patch/timer/dev/8bit-async-mega8.yaml b/patch/timer/dev/8bit-async-mega8.yaml index ef2e71c39e768183a7eb3b1957e0edc6b342c512..7d05f4efb815d0382b92eb859c5b22802d443eb2 100644 --- a/patch/timer/dev/8bit-async-mega8.yaml +++ b/patch/timer/dev/8bit-async-mega8.yaml @@ -2,8 +2,6 @@ TCCR?: _modify: COM?: _write_constraint: enum - WGM?: - _write_constraint: enum FOC?: access: write-only COM?: @@ -11,16 +9,6 @@ TCCR?: DISCONNECTED: [0, "Normal port operation, OC2 disconnected"] MATCH_CLEAR: [2, "Clear OC2 on Compare Match (If PWM is enabled, OC2 is set at BOTTOM)"] MATCH_SET: [3, "Set OC2 on Compare Match (If PWM is enabled, OC2 is cleared at BOTTOM)"] - WGM?: - _replace_enum: - # NOTE that the WGMs are in reverse order in the reigster - # (WGM20 is at position 6, WGM21 is at position 3), thus - # the numbering here is not the same as in datasheet - # where it is specified for WGM21 WGM20 - NORMAL_TOP: [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"] - PWM_PHASE: [2, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"] - CTC: [1, "CTC, Top: *OCR2*, Update: *Immediate*, Flag: *MAX*"] - PWM_FAST: [3, "Fast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *MAX*"] CS?: _replace_enum: NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] diff --git a/vendor/atmega8.atdf b/vendor/atmega8.atdf index 5edc055088aac4d2e49ac18443f6f296591ce541..1295212b529d1720eefc176d2ee5e1749e5d18f4 100644 --- a/vendor/atmega8.atdf +++ b/vendor/atmega8.atdf @@ -629,8 +629,9 @@ - + +