From 77a1d54401d70044b977a991ebf44feb731d9709 Mon Sep 17 00:00:00 2001
From: Rahix <rahix@rahix.de>
Date: Wed, 29 Jul 2020 22:36:47 +0200
Subject: [PATCH] atmega32u4: Add patch for 10-bit timer/counter

Signed-off-by: Rahix <rahix@rahix.de>
---
 patch/timer/atmega32u4.yaml |  4 +++
 patch/timer/dev/10bit.yaml  | 56 +++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 patch/timer/dev/10bit.yaml

diff --git a/patch/timer/atmega32u4.yaml b/patch/timer/atmega32u4.yaml
index 11cc96f..33ad7ee 100644
--- a/patch/timer/atmega32u4.yaml
+++ b/patch/timer/atmega32u4.yaml
@@ -8,3 +8,7 @@ TC0:
 TC1,TC3:
   _include:
     - "dev/16bit.yaml"
+
+TC4:
+  _include:
+    - "dev/10bit.yaml"
diff --git a/patch/timer/dev/10bit.yaml b/patch/timer/dev/10bit.yaml
new file mode 100644
index 0000000..c413548
--- /dev/null
+++ b/patch/timer/dev/10bit.yaml
@@ -0,0 +1,56 @@
+TCCR?A,TCCR?C:
+  _modify:
+    FOC??:
+      access: write-only
+    COM??:
+      _write_constraint: enum
+  COM??:
+    _replace_enum:
+        DISCONNECTED:  [0, "Normal port operation, OCix disconnected"]
+        MATCH_TOGGLE:  [1, "Toggle OCix on Compare Match (Might depend on WGM)"]
+        MATCH_CLEAR:   [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)"]
+        MATCH_SET:     [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)"]
+
+TCCR?B:
+  _modify:
+    CS?:
+      _write_constraint: enum
+  CS?:
+    _replace_enum:
+      NO_CLOCK:       [0,  "No clock source (Timer/Counter stopped)"]
+      DIRECT:         [1,  "Running, No Prescaling"]
+      PRESCALE_2:     [2,  "Running, CLK/2"]
+      PRESCALE_4:     [3,  "Running, CLK/4"]
+      PRESCALE_8:     [4,  "Running, CLK/8"]
+      PRESCALE_16:    [5,  "Running, CLK/16"]
+      PRESCALE_32:    [6,  "Running, CLK/32"]
+      PRESCALE_64:    [7,  "Running, CLK/64"]
+      PRESCALE_128:   [8,  "Running, CLK/128"]
+      PRESCALE_256:   [9,  "Running, CLK/256"]
+      PRESCALE_512:   [10, "Running, CLK/512"]
+      PRESCALE_1024:  [11, "Running, CLK/1024"]
+      PRESCALE_2048:  [12, "Running, CLK/2048"]
+      PRESCALE_4096:  [13, "Running, CLK/4096"]
+      PRESCALE_8192:  [14, "Running, CLK/8192"]
+      PRESCALE_16384: [15, "Running, CLK/16384"]
+  DTPS?:
+    _replace_enum:
+      X1: [0, "1x (no division)"]
+      X2: [1, "2x"]
+      X4: [2, "4x"]
+      X8: [3, "8x"]
+
+TCCR?D:
+  _modify:
+    WGM?:
+      _write_constraint: enum
+  WGM?:
+    _replace_enum:
+      PWM_FAST:         [0, "Fast PWM, Update: *TOP*, Flag: *TOP*"]
+      PWM_CORRECT:      [1, "Phase and Frequency Correct PWM, Update: *BOTTOM*, Flag: *BOTTOM*"]
+      PWM_SINGLE_SLOPE: [2, "PWM6 / Single-slope, Update: *TOP*, Flag: *TOP*"]
+      PWM_DUAL_SLOPE:   [3, "PWM6 / Dual-slope, Update: *BOTTOM*, Flag: *BOTTOM*"]
+
+_modify:
+  TC?H:
+    description: Timer/Counter High Bits
-- 
2.48.1