From 1606c20e1c9b003dd0bed6694c2ac09b70ab1f4d Mon Sep 17 00:00:00 2001
From: Jonah Dahlquist <jonah@jonah.name>
Date: Tue, 25 Jun 2019 08:05:16 -0500
Subject: [PATCH] common: Fix a few patches

- Fix some descriptions
- Rename ambiguous WDT options
---
 patch/common/timer/tc0.yaml |  2 ++
 patch/common/usart.yaml     |  2 ++
 patch/common/wdt.yaml       | 16 ++++++++--------
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/patch/common/timer/tc0.yaml b/patch/common/timer/tc0.yaml
index 4e194d1..c7b0048 100644
--- a/patch/common/timer/tc0.yaml
+++ b/patch/common/timer/tc0.yaml
@@ -2,8 +2,10 @@ TC0:
   TCCR0A:
     _modify:
       COM0A:
+        description: "Compare Output A Mode"
         _write_constraint: enum
       COM0B:
+        description: "Compare Output B Mode"
         _write_constraint: enum
       WGM0:
         _write_constraint: enum
diff --git a/patch/common/usart.yaml b/patch/common/usart.yaml
index 7a3d0f3..59f2cbf 100644
--- a/patch/common/usart.yaml
+++ b/patch/common/usart.yaml
@@ -12,6 +12,8 @@ USART?:
         access: read-only
       UDRE?:
         access: read-only
+      TXC?:
+        description: "USART Transmit Complete"
       RXC?:
         access: read-only
   UCSR?B:
diff --git a/patch/common/wdt.yaml b/patch/common/wdt.yaml
index e3a5a23..e4ba06d 100644
--- a/patch/common/wdt.yaml
+++ b/patch/common/wdt.yaml
@@ -22,11 +22,11 @@ WDT:
         description: "Watchdog Timer Prescaler - High Bit"
         bitRange: "[5:5]"
     WDPL:
-      CYCLES_2K:     [0, "- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set"]
-      CYCLES_4K:     [1, "- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set"]
-      CYCLES_8K:     [2, "- 8192 cycles, ~64ms"]
-      CYCLES_16K:    [3, "- 16K (16384) cycles, ~0.125s"]
-      CYCLES_32K:    [4, "- 32K (32768) cycles, ~0.25s"]
-      CYCLES_64K:    [5, "- 64K (65536) cycles, ~0.5s"]
-      CYCLES_128K:   [6, "- 128K (131072) cycles, ~1s"]
-      CYCLES_256K:   [7, "- 256K (262144) cycles, ~2s"]
+      CYCLES_2K_512K:  [0, "- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set"]
+      CYCLES_4K_1024K: [1, "- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set"]
+      CYCLES_8K:       [2, "- 8192 cycles, ~64ms"]
+      CYCLES_16K:      [3, "- 16K (16384) cycles, ~0.125s"]
+      CYCLES_32K:      [4, "- 32K (32768) cycles, ~0.25s"]
+      CYCLES_64K:      [5, "- 64K (65536) cycles, ~0.5s"]
+      CYCLES_128K:     [6, "- 128K (131072) cycles, ~1s"]
+      CYCLES_256K:     [7, "- 256K (262144) cycles, ~2s"]
-- 
2.48.1