From 0f1b031aa3d1b69089e77d9bd90500b1ec44b225 Mon Sep 17 00:00:00 2001 From: Rahix Date: Sat, 11 May 2019 23:38:27 +0200 Subject: [PATCH] atmega32u4: Add patch for PLL Signed-off-by: Rahix --- patch/atmega32u4.yaml | 1 + patch/common/pll.yaml | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 patch/common/pll.yaml diff --git a/patch/atmega32u4.yaml b/patch/atmega32u4.yaml index 78bc50c..0cc5e72 100644 --- a/patch/atmega32u4.yaml +++ b/patch/atmega32u4.yaml @@ -1,3 +1,4 @@ _include: - "common/ac.yaml" + - "common/pll.yaml" - "common/twi.yaml" diff --git a/patch/common/pll.yaml b/patch/common/pll.yaml new file mode 100644 index 0000000..9d5597f --- /dev/null +++ b/patch/common/pll.yaml @@ -0,0 +1,34 @@ +PLL: + PLLCSR: + _modify: + PLOCK: + access: read-only + PLLFRQ: + _delete: + - PDIV + - PLLTM + _modify: + PINMUX: + description: "PLL Input Multiplexer" + PLLUSB: + description: "PLL Postcaler for USB Peripheral" + _add: + PDIV: + description: "PLL Lock Frequency" + bitRange: "[3:0]" + PLLTM: + description: "PLL Postcaler for High Speed Timer" + bitRange: "[5:4]" + PDIV: + MHZ40: [0b0011, "40 MHz"] + MHZ48: [0b0100, "48 MHz"] + MHZ56: [0b0101, "56 MHz"] + MHZ72: [0b0111, "72 MHz"] + MHZ80: [0b1000, "80 MHz"] + MHZ88: [0b1001, "88 MHz"] + MHZ96: [0b1010, "96 MHz"] + PLLTM: + DISCONNECTED: [0, "0 (Disconnected)"] + FACTOR_1: [1, "1"] + FACTOR_15: [2, "1.5"] + FACTOR_2: [3, "2"] -- 2.49.0